Wonkyu Kim 528ae9e811 soc/tigerlake: Correct FSP log interface ... Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-03-02 23:43:12 +00:00
..
apollolake	soc/intel/apollolake: Fix flashconsole, again	2020-03-02 11:49:50 +00:00
baytrail	treewide: Capitalize 'CMOS'	2020-02-24 14:10:00 +00:00
braswell	treewide: Capitalize 'CMOS'	2020-02-24 14:10:00 +00:00
broadwell	treewide: Capitalize 'CMOS'	2020-02-24 14:10:00 +00:00
cannonlake	soc/intel/{common, skl, cnl, apl}: Move print_me_fw_version() to CSE lib	2020-03-02 11:38:18 +00:00
common	soc/intel/{common, skl, cnl, apl}: Move print_me_fw_version() to CSE lib	2020-03-02 11:38:18 +00:00
denverton_ns	soc/intel/denverton/uart.c: Clean up code	2020-03-02 19:13:39 +00:00
icelake	soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig	2020-03-01 07:21:41 +00:00
quark	soc/intel: Add get_pmbase	2020-02-04 18:54:01 +00:00
skylake	soc/intel/{common, skl, cnl, apl}: Move print_me_fw_version() to CSE lib	2020-03-02 11:38:18 +00:00
tigerlake	soc/tigerlake: Correct FSP log interface	2020-03-02 23:43:12 +00:00
Kconfig	soc/intel/Kconfig: Load Tiger Lake SOC Kconfig	2019-12-11 11:37:45 +00:00