125 lines
4.3 KiB
Markdown
125 lines
4.3 KiB
Markdown
Upcoming release - coreboot 4.11
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================================
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The 4.11 release is planned for October 2019
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Update this document with changes that should be in the release
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notes.
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* Please use Markdown.
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* See the [4.9](coreboot-4.9-relnotes.md) and [4.10](coreboot-4.10-relnotes.md)
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release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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Clean Up
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--------
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Because there was only a single developer board (AMD Torpedo)
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using AGESA family 12h, and because there were multiple,
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unique Coverity issues with it, the associated vendorcode will
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be removed shortly after this release.
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Support for the MIPS architecture will also be removed shortly after
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this release as the only board in the tree was a discontinued development
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board and no other work has picked up MIPS support, so it's very likely
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broken already.
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Significant changes
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-------------------
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### `__PRE_RAM__` is deprecated
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Preprocessor use of `defined(__PRE_RAM__)` have been mostly replaced with
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`if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`.
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The remaining cases and `-D__PRE_RAM__` are to be removed soon after release.
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### `__BOOTBLOCK__` et.al. are converted
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This applies to all `ENV_xxx` definitions found in `<rules.h>`.
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Write code without preprocessor directives whenever possible, replacing
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`#ifdef __BOOTBLOCK__` with `if (ENV_BOOTBLOCK)`
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In cases where preprocessor is needed use `#if ENV_BOOTBLOCK` instead.
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### `CAR_GLOBAL` is removed where possible
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For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL`
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attributes have been removed. Remaining cases from common code are to be
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removed soon after release.
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### `TSEG` and `cbmem_top()` mapping
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Significant refactoring has bee done to achieve some consistency across platforms
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and to reduce code duplication.
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### Build system amenities ###
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The build system now has an `all` class of source files to remove the need to
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list source files for each and every source class (romstage, ramstage, ...)
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The site-local/ mechanism became more robust.
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### Stricter coding standards to improve security ###
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The build now fails on variable length arrays (that make it way too easy to
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smash a stack) and case statements falling through without a note that it is
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intentional.
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### Shorter file headers ###
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This project is still under way, but we started moving author information
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from individual files into the global AUTHORS file (and there's the git
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history for more details).
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In the future, we also want to replace the license headers (lots of lines)
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in each file with spdx identifiers (one line) and so we added a LICENSES/
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directory that contains the full text of all the licenses that are used
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throughout our tree.
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### Variant creation scripts ###
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To ease the creation of variant boards, `util/mainboard/` now contains
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scripts to generate a new variant to a given board. These are still
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specific to google/hatch at this time, but they're written with the idea
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of becoming more generally useful.
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### Payloads ###
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Payload integration has been updated, coreinfo learned to cope with
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UPPER CASE commands and libpayload knows how to deal with USB3 hubs.
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### Added VBOOT support to the following platforms:
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* intel/gm45
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* intel/nehalem
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### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK:
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* intel/i945
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* intel/x4x
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* intel/gm45
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* intel/nehalem
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* intel/braswell
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### libgfxinit ###
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Most notable, dynamic CDClk configuration was added to libgfxinit,
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to support higher resolution displays without changes in the static
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configuration. It also received some fixes for better DP and eDP
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compatibility, better error recovery for Intel's fickle GMBus and
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updated platform support:
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* Correct HDMI clock limit for G45.
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* DP support for Ibex Peak (Ironlake graphics).
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* Fixed scaling on eDP for Broadwell.
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* Support for ULX variants of Haswell and later.
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* Support for Kaby, Amber, Coffee and Whiskey Lake.
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### Other
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* Did cleanups around TSC timer
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* Improved automatic VR configuration on SKL/KBL
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* Filled additional fields in SMBIOS type 4
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* Removed magic value replay from Intel Nehalem/ibexpeak code base
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* Added OpenSBI on RISCV platforms
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* Did more preparations for Intel TXT support
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* Did more preparations for x86_64 stage support
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* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb
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