dd59762729
Also fix wrong 32-bit writes. Change-Id: Ib038f0cd558223536da08ba2264774db11cd8357 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40727 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
610 lines
17 KiB
C
610 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <bootmode.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <string.h>
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#include <reg_script.h>
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#include <drivers/intel/gma/i915.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <drivers/intel/gma/libgfxinit.h>
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#include <drivers/intel/gma/opregion.h>
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#include <soc/cpu.h>
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#include <soc/pm.h>
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#include <soc/ramstage.h>
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#include <soc/systemagent.h>
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#include <soc/intel/broadwell/chip.h>
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#include <security/vboot/vbnv.h>
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#include <soc/igd.h>
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#include <types.h>
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#define GT_RETRY 1000
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enum {
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GT_CDCLK_DEFAULT = 0,
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GT_CDCLK_337,
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GT_CDCLK_450,
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GT_CDCLK_540,
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GT_CDCLK_675,
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};
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static u32 reg_em4;
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static u32 reg_em5;
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u32 igd_get_reg_em4(void) { return reg_em4; }
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u32 igd_get_reg_em5(void) { return reg_em5; }
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struct reg_script haswell_early_init_script[] = {
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/* Enable Force Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
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/* Enable Counters */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
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/* GFXPAUSE settings */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020),
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/* ECO Settings */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000),
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/* Enable DOP Clock Gating */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd),
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/* Enable Unit Level Clock Gating */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
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/*
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* RC6 Settings
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*/
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/* Wake Rate Limits */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa090, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa098, 0x03e80000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa09c, 0x00280000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0a8, 0x0001e848),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0ac, 0x00000019),
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/* Render/Video/Blitter Idle Max Count */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a),
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/* RC Sleep / RCx Thresholds */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b0, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b4, 0x000003e8),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b8, 0x0000c350),
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/* RP Settings */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa010, 0x000f4240),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa014, 0x12060000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa02c, 0x0000e808),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa030, 0x0003bd08),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa068, 0x000101d0),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa06c, 0x00055730),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a),
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/* RP Control */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92),
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/* HW RC6 Control */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x88040000),
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/* Video Frequency Request */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
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/* Set RC6 VIDs */
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
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/* Enable PM Interrupts */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
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/* Enable RC6 in idle */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000),
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REG_SCRIPT_END
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};
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static const struct reg_script haswell_late_init_script[] = {
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/* Lock settings */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a004, (1 << 4)),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a080, (1 << 2)),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)),
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/* Disable Force Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
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/* Enable power well for DP and Audio */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
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(1 << 30), (1 << 30), GT_RETRY),
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REG_SCRIPT_END
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};
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static const struct reg_script broadwell_early_init_script[] = {
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/* Enable Force Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
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/* Enable push bus metric control and shift */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010),
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/* GFXPAUSE settings (set based on stepping) */
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/* ECO Settings */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000),
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/* Enable DOP Clock Gating */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000000fd),
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/* Enable Unit Level Clock Gating */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000000),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a),
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/* Video Frequency Request */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138158, 0x00000009),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x13815c, 0x0000000d),
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/*
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* RC6 Settings
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*/
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/* Wake Rate Limits */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0a090, 0, 0),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a098, 0x03e80000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a09c, 0x00280000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0a8, 0x0001e848),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0ac, 0x00000019),
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/* Render/Video/Blitter Idle Max Count */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a),
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/* RC Sleep / RCx Thresholds */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b0, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b8, 0x00000271),
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/* RP Settings */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a010, 0x000f4240),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a014, 0x12060000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a02c, 0x0000e808),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a030, 0x0003bd08),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a068, 0x000101d0),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a06c, 0x00055730),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a070, 0x0000000a),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a168, 0x00000006),
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/* RP Control */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92),
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/* HW RC6 Control */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
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/* Set RC6 VIDs */
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
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/* Enable PM Interrupts */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
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/* Enable RC6 in idle */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000),
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REG_SCRIPT_END
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};
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static const struct reg_script broadwell_late_init_script[] = {
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/* Lock settings */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a000, (1 << 18)),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)),
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/* Disable Force Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
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/* Enable power well for DP and Audio */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
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(1 << 30), (1 << 30), GT_RETRY),
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REG_SCRIPT_END
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};
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u32 map_oprom_vendev(u32 vendev)
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{
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return SA_IGD_OPROM_VENDEV;
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}
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static struct resource *gtt_res = NULL;
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u32 gtt_read(u32 reg)
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{
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u32 val;
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val = read32(res2mmio(gtt_res, reg, 0));
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return val;
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}
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void gtt_write(u32 reg, u32 data)
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{
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write32(res2mmio(gtt_res, reg, 0), data);
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}
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static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
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{
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u32 val = gtt_read(reg);
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val &= andmask;
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val |= ormask;
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gtt_write(reg, val);
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}
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int gtt_poll(u32 reg, u32 mask, u32 value)
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{ unsigned int try = GT_RETRY;
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u32 data;
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while (try--) {
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data = gtt_read(reg);
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if ((data & mask) == value)
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return 1;
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udelay(10);
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}
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printk(BIOS_ERR, "GT init timeout\n");
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return 0;
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}
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static void igd_setup_panel(struct device *dev)
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{
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config_t *conf = config_of(dev);
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u32 reg32;
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/* Setup Digital Port Hotplug */
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reg32 = gtt_read(PCH_PORT_HOTPLUG);
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if (!reg32) {
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reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
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reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
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reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
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gtt_write(PCH_PORT_HOTPLUG, reg32);
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}
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/* Setup Panel Power On Delays */
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reg32 = gtt_read(PCH_PP_ON_DELAYS);
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if (!reg32) {
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reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
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reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
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reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
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gtt_write(PCH_PP_ON_DELAYS, reg32);
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}
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/* Setup Panel Power Off Delays */
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reg32 = gtt_read(PCH_PP_OFF_DELAYS);
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if (!reg32) {
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reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
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reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
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gtt_write(PCH_PP_OFF_DELAYS, reg32);
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}
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/* Setup Panel Power Cycle Delay */
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if (conf->gpu_panel_power_cycle_delay) {
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reg32 = gtt_read(PCH_PP_DIVISOR);
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reg32 &= ~0xff;
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reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
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gtt_write(PCH_PP_DIVISOR, reg32);
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}
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/* So far all devices seem to use the PCH PWM function.
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The CPU PWM registers are all zero after reset. */
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if (conf->gpu_pch_backlight_pwm_hz) {
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/* For Lynx Point-LP:
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Reference clock is 24MHz. We can choose either a 16
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or a 128 step increment. Use 16 if we would have less
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than 100 steps otherwise. */
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const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
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unsigned int pwm_increment, pwm_period;
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u32 south_chicken2;
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south_chicken2 = gtt_read(SOUTH_CHICKEN2);
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if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
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pwm_increment = 16;
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south_chicken2 |= 1 << 5;
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} else {
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pwm_increment = 128;
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south_chicken2 &= ~(1 << 5);
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}
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gtt_write(SOUTH_CHICKEN2, south_chicken2);
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pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
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/* Start with a 50% duty cycle. */
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gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
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gtt_write(BLC_PWM_PCH_CTL1,
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(conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
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BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
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}
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}
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static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
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struct device *const dev)
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{
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const config_t *const conf = config_of(dev);
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int cdclk = conf->cdclk;
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/* Check for ULX GT1 or GT2 */
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const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
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const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 ||
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devid == IGD_HASWELL_ULX_GT2;
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/* Check for fixed fused clock */
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if (gtt_read(0x42014) & 1 << 24)
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cdclk = GT_CDCLK_450;
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/*
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* ULX defaults to 337MHz with possible override for 450MHz
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* ULT is fixed at 450MHz
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* others default to 540MHz with possible override for 450MHz
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*/
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if (gpu_is_ulx && cdclk <= GT_CDCLK_337)
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cdclk = GT_CDCLK_337;
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else if (gpu_is_ulx || cpu_is_ult() ||
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cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450)
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cdclk = GT_CDCLK_450;
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else
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cdclk = GT_CDCLK_540;
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*cdsel = cdclk != GT_CDCLK_450;
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*inform_pc = gpu_is_ulx;
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return cdclk;
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}
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static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc,
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struct device *const dev)
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{
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static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 };
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const config_t *const conf = config_of(dev);
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int cdclk = conf->cdclk;
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/* Check for ULX */
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const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
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const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2;
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/* Inform power controller of upcoming frequency change */
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gtt_write(0x138128, 0);
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gtt_write(0x13812c, 0);
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gtt_write(0x138124, 0x80000018);
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/* Poll GT driver mailbox for run/busy clear */
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if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
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*inform_pc = 1;
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} else {
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cdclk = GT_CDCLK_450;
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*inform_pc = 0;
|
|
}
|
|
|
|
/* Check for fixed fused clock */
|
|
if (gtt_read(0x42014) & 1 << 24)
|
|
cdclk = GT_CDCLK_450;
|
|
|
|
/*
|
|
* ULX defaults to 450MHz with possible override up to 540MHz
|
|
* ULT defaults to 540MHz with possible override up to 675MHz
|
|
* others default to 675MHz with possible override for lower freqs
|
|
*/
|
|
if (cdclk == GT_CDCLK_337)
|
|
cdclk = GT_CDCLK_337;
|
|
else if (cdclk == GT_CDCLK_450 ||
|
|
(gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT))
|
|
cdclk = GT_CDCLK_450;
|
|
else if (cdclk == GT_CDCLK_540 || gpu_is_ulx ||
|
|
(cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT))
|
|
cdclk = GT_CDCLK_540;
|
|
else
|
|
cdclk = GT_CDCLK_675;
|
|
|
|
*cdsel = cdsel_by_cdclk[cdclk];
|
|
return cdclk;
|
|
}
|
|
|
|
static void igd_cdclk_init(struct device *dev, const int is_broadwell)
|
|
{
|
|
u32 dpdiv, cdsel, cdval;
|
|
int cdclk, inform_pc;
|
|
|
|
if (is_broadwell)
|
|
cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev);
|
|
else
|
|
cdclk = igd_get_cdclk_haswell(&cdsel, &inform_pc, dev);
|
|
|
|
/* Set variables based on CD Clock setting */
|
|
switch (cdclk) {
|
|
case GT_CDCLK_337:
|
|
cdval = 337;
|
|
dpdiv = 169;
|
|
reg_em4 = 16;
|
|
reg_em5 = 225;
|
|
break;
|
|
case GT_CDCLK_450:
|
|
cdval = 449;
|
|
dpdiv = 225;
|
|
reg_em4 = 4;
|
|
reg_em5 = 75;
|
|
break;
|
|
case GT_CDCLK_540:
|
|
cdval = 539;
|
|
dpdiv = 270;
|
|
reg_em4 = 4;
|
|
reg_em5 = 90;
|
|
break;
|
|
case GT_CDCLK_675:
|
|
cdval = 674;
|
|
dpdiv = 338;
|
|
reg_em4 = 8;
|
|
reg_em5 = 225;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
/* Set LPCLL_CTL CD Clock Frequency Select */
|
|
gtt_rmw(0x130040, 0xf3ffffff, cdsel << 26);
|
|
|
|
if (inform_pc) {
|
|
/* Inform power controller of selected frequency */
|
|
gtt_write(0x138128, cdsel);
|
|
gtt_write(0x13812c, 0);
|
|
gtt_write(0x138124, 0x80000017);
|
|
}
|
|
|
|
/* Program CD Clock Frequency */
|
|
gtt_rmw(0x46200, 0xfffffc00, cdval);
|
|
|
|
/* Set CPU DP AUX 2X bit clock dividers */
|
|
gtt_rmw(0x64010, 0xfffff800, dpdiv);
|
|
gtt_rmw(0x64810, 0xfffff800, dpdiv);
|
|
}
|
|
|
|
static void igd_init(struct device *dev)
|
|
{
|
|
int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
|
|
u32 rp1_gfx_freq;
|
|
|
|
intel_gma_init_igd_opregion();
|
|
|
|
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
|
if (!gtt_res || !gtt_res->base)
|
|
return;
|
|
|
|
if (!CONFIG(NO_GFX_INIT))
|
|
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
|
|
|
|
/* Wait for any configured pre-graphics delay */
|
|
if (!acpi_is_wakeup_s3()) {
|
|
#if CONFIG(CHROMEOS)
|
|
if (display_init_required())
|
|
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
|
|
#else
|
|
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
|
|
#endif
|
|
}
|
|
|
|
/* Early init steps */
|
|
if (is_broadwell) {
|
|
reg_script_run_on_dev(dev, broadwell_early_init_script);
|
|
|
|
/* Set GFXPAUSE based on stepping */
|
|
if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
|
|
systemagent_revision() <= 9) {
|
|
gtt_write(0xa000, 0x300ff);
|
|
} else {
|
|
gtt_write(0xa000, 0x30020);
|
|
}
|
|
} else {
|
|
reg_script_run_on_dev(dev, haswell_early_init_script);
|
|
}
|
|
|
|
/* Set RP1 graphics frequency */
|
|
rp1_gfx_freq = (MCHBAR32(0x5998) >> 8) & 0xff;
|
|
gtt_write(0xa008, rp1_gfx_freq << 24);
|
|
|
|
/* Post VBIOS panel setup */
|
|
igd_setup_panel(dev);
|
|
|
|
/* Initialize PCI device, load/execute BIOS Option ROM */
|
|
pci_dev_init(dev);
|
|
|
|
/* Late init steps */
|
|
igd_cdclk_init(dev, is_broadwell);
|
|
if (is_broadwell)
|
|
reg_script_run_on_dev(dev, broadwell_late_init_script);
|
|
else
|
|
reg_script_run_on_dev(dev, haswell_late_init_script);
|
|
|
|
if (gfx_get_init_done()) {
|
|
/*
|
|
* Work around VBIOS issue that is not clearing first 64
|
|
* bytes of the framebuffer during VBE mode set.
|
|
*/
|
|
struct resource *fb = find_resource(dev, PCI_BASE_ADDRESS_2);
|
|
memset((void *)((u32)fb->base), 0, 64);
|
|
}
|
|
|
|
if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) {
|
|
/*
|
|
* Enable DDI-A if the Option ROM did not execute:
|
|
*
|
|
* bit 0: Display detected (RO)
|
|
* bit 4: DDI A supports 4 lanes and DDI E is not used
|
|
* bit 7: DDI buffer is idle
|
|
*/
|
|
gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
|
|
DDI_INIT_DISPLAY_DETECTED);
|
|
}
|
|
|
|
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
|
|
int lightup_ok;
|
|
gma_gfxinit(&lightup_ok);
|
|
gfx_set_init_done(lightup_ok);
|
|
}
|
|
}
|
|
|
|
static void gma_generate_ssdt(const struct device *dev)
|
|
{
|
|
const struct soc_intel_broadwell_config *chip = dev->chip_info;
|
|
|
|
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
|
|
}
|
|
|
|
static struct device_operations igd_ops = {
|
|
.read_resources = &pci_dev_read_resources,
|
|
.set_resources = &pci_dev_set_resources,
|
|
.enable_resources = &pci_dev_enable_resources,
|
|
.init = &igd_init,
|
|
.ops_pci = &broadwell_pci_ops,
|
|
.acpi_fill_ssdt = gma_generate_ssdt,
|
|
};
|
|
|
|
static const unsigned short pci_device_ids[] = {
|
|
IGD_HASWELL_ULT_GT1,
|
|
IGD_HASWELL_ULT_GT2,
|
|
IGD_HASWELL_ULT_GT3,
|
|
IGD_BROADWELL_U_GT1,
|
|
IGD_BROADWELL_U_GT2,
|
|
IGD_BROADWELL_U_GT3_15W,
|
|
IGD_BROADWELL_U_GT3_28W,
|
|
IGD_BROADWELL_Y_GT2,
|
|
IGD_BROADWELL_H_GT2,
|
|
IGD_BROADWELL_H_GT3,
|
|
0,
|
|
};
|
|
|
|
static const struct pci_driver igd_driver __pci_driver = {
|
|
.ops = &igd_ops,
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.devices = pci_device_ids,
|
|
};
|