81ae67a634
Combine existing board google/panther with new ChromeOS devices mccloud, monroe, tricky, and zako, using their common reference board (beltino) as a base. Chromium sources used: firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...] firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.] firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...] firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...] Existing google/panther board will be removed in a subsequent commit. Variant setup modeled after google/reef Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17329 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <cpu/x86/smm.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <southbridge/intel/lynxpoint/me.h>
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#include <southbridge/intel/lynxpoint/nvs.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <elog.h>
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#include <superio/ite/it8772f/it8772f.h>
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#include "onboard.h"
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static int mainboard_finalized = 0;
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int mainboard_smi_apmc(u8 apmc)
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{
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switch (apmc) {
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case APM_CNT_FINALIZE:
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if (mainboard_finalized) {
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printk(BIOS_DEBUG, "SMI#: Already finalized\n");
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return 0;
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}
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intel_pch_finalize_smm();
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intel_northbridge_haswell_finalize_smm();
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intel_cpu_haswell_finalize_smm();
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mainboard_finalized = 1;
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break;
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default:
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break;
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}
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return 0;
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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switch (slp_typ) {
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case ACPI_S3:
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set_power_led(LED_BLINK);
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break;
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case ACPI_S4:
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case ACPI_S5:
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set_power_led(LED_OFF);
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break;
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default:
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break;
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}
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return;
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}
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