261b893b7c
This patch ensures all soc function name is having _soc_ prefix in it. TEST=Able to compile SMM common code for all supported SOC. Change-Id: Iab1b2f51eaad87906e35dbb9e90272590974e145 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015-2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/smihandler.h>
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#include <soc/pm.h>
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const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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void smihandler_soc_check_illegal_access(uint32_t tco_sts)
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{
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if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)
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&& fast_spi_wpd_status()))
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return;
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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fast_spi_enable_wp();
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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[PM1_STS_BIT] = smihandler_southbridge_pm1,
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[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
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[GPIO_STS_BIT] = smihandler_southbridge_gpi,
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[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
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[MCSMI_STS_BIT] = smihandler_southbridge_mc,
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[TCO_STS_BIT] = smihandler_southbridge_tco,
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[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
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[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
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};
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