682613f065
This adds delivery of PIC/i8259 interrupts via ExtNMI on the affected platfoms. Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
547 lines
15 KiB
C
547 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <arch/ioapic.h>
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#include <acpi/acpi.h>
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#include <cpu/x86/smm.h>
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#include <bootstate.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/iomap.h>
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#include <soc/pcr.h>
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#include <soc/p2sb.h>
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#include <soc/acpi.h>
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#include "chip.h"
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/* PCH I/O APIC redirection entries */
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#define PCH_REDIR_ETR 120
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/**
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* Set miscellaneous static southbridge features.
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*
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* @param dev PCI device with I/O APIC control registers
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*/
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static void pch_enable_ioapic(struct device *dev)
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{
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/* affirm full set of redirection table entries ("write once") */
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ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
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setup_ioapic((void *)IO_APIC_ADDR, IO_APIC0);
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}
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/* interrupt router lookup for internal devices */
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struct dnv_ir_lut {
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/* (dev << 3) | fn */
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u8 devfn;
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u8 ir;
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};
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#define DEVFN(dev, fn) ((dev << 3) | (fn))
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static const struct dnv_ir_lut dnv_ir_lut[] = {
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{.devfn = DEVFN(0x05, 0), .ir = 3}, /* RCEC */
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{.devfn = DEVFN(0x06, 0), .ir = 4}, /* Virtual RP to QAT */
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{.devfn = DEVFN(0x09, 0), .ir = 7}, /* PCIe RP0 */
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{.devfn = DEVFN(0x0a, 0), .ir = 7}, /* PCIe RP1 */
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{.devfn = DEVFN(0x0b, 0), .ir = 7}, /* PCIe RP2 */
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{.devfn = DEVFN(0x0c, 0), .ir = 7}, /* PCIe RP3 */
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{.devfn = DEVFN(0x0e, 0), .ir = 8}, /* PCIe RP4 */
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{.devfn = DEVFN(0x0f, 0), .ir = 8}, /* PCIe RP5 */
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{.devfn = DEVFN(0x10, 0), .ir = 8}, /* PCIe RP6 */
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{.devfn = DEVFN(0x11, 0), .ir = 8}, /* PCIe RP7 */
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{.devfn = DEVFN(0x12, 0), .ir = 10}, /* SMBus - Host */
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{.devfn = DEVFN(0x13, 0), .ir = 6}, /* AHCI0 */
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{.devfn = DEVFN(0x14, 0), .ir = 11}, /* AHCI1 */
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{.devfn = DEVFN(0x15, 0), .ir = 9}, /* USB */
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{.devfn = DEVFN(0x16, 0), .ir = 1}, /* Virtual RP to LAN0 */
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{.devfn = DEVFN(0x17, 0), .ir = 2}, /* Virtual RP to LAN1 */
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{.devfn = DEVFN(0x18, 0), .ir = 5}, /* ME HECI1 */
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{.devfn = DEVFN(0x18, 1), .ir = 5}, /* ME HECI1 */
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{.devfn = DEVFN(0x18, 2), .ir = 5}, /* ME PTIO-IDER */
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{.devfn = DEVFN(0x18, 3), .ir = 5}, /* ME PTIO-KT */
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{.devfn = DEVFN(0x18, 4), .ir = 5}, /* ME HECI3 */
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{.devfn = DEVFN(0x1a, 0), .ir = 10}, /* HSUART0 */
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{.devfn = DEVFN(0x1a, 1), .ir = 10}, /* HSUART1 */
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{.devfn = DEVFN(0x1a, 2), .ir = 10}, /* HSUART2 */
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{.devfn = DEVFN(0x1b, 0), .ir = 12}, /* IE HECI1 */
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{.devfn = DEVFN(0x1b, 1), .ir = 12}, /* IE HECI1 */
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{.devfn = DEVFN(0x1b, 2), .ir = 12}, /* IE PTIO-IDER */
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{.devfn = DEVFN(0x1b, 3), .ir = 12}, /* IE PTIO-KT */
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{.devfn = DEVFN(0x1b, 4), .ir = 12}, /* IE HECI3 */
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{.devfn = DEVFN(0x1c, 0), .ir = 12}, /* SDHCI */
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{.devfn = DEVFN(0x1f, 0), .ir = 0}, /* LPC */
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{.devfn = DEVFN(0x1f, 1), .ir = 0}, /* PS2B */
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{.devfn = DEVFN(0x1f, 4), .ir = 0}, /* SMBus - Legacy */
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{.devfn = DEVFN(0x1f, 7), .ir = 0}, /* Trace Hub */
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};
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/*
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* Only 6 of the 8 root ports have swizzling, return '1' if this bdf is one of
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* them, '0' otherwise
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*/
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static int is_dnv_swizzled_rp(uint16_t bdf)
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{
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switch (bdf) {
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case DEVFN(10, 0):
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case DEVFN(11, 0):
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case DEVFN(12, 0):
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case DEVFN(15, 0):
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case DEVFN(16, 0):
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case DEVFN(17, 0):
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return 1;
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}
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return 0;
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}
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/*
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* Figure out which upstream interrupt pin a downstream device gets swizzled to
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*
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* config - pointer to chip_info containing routing info
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* devfn - device/function of root port to check swizzling for
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* pin - interrupt pin 1-4 = A-D
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*
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* Return new pin mapping, 0 if invalid pin
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*/
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static int dnv_get_swizzled_pin(config_t *config, u8 devfn, u8 pin)
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{
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if (pin < 1 || pin > 4)
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return 0;
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devfn >>= 3;
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if (devfn < 13)
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devfn -= 9;
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else
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devfn -= 14;
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return ((pin - 1 + devfn) % 4) + 1;
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}
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/*
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* Figure out which upstream interrupt pin a downstream device gets swizzled to
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*
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* config - pointer to chip_info containing routing info
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* devfn - device/function of root port to check swizzling for
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* pin - interrupt pin 1-4 = A-D
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*
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* Return new pin mapping, 0 if invalid pin
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*/
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static int dnv_get_ir(config_t *config, u8 devfn, u8 pin)
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{
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int i = 0;
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int line = 0xff;
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u16 ir = 0xffff;
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/* The only valid pin values are 1-4 for A-D */
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if (pin < 1 || pin > 4) {
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printk(BIOS_WARNING, "%s: pin %d is invalid\n", __func__, pin);
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goto dnv_get_ir_done;
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}
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for (i = 0; i < ARRAY_SIZE(dnv_ir_lut); i++) {
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if (dnv_ir_lut[i].devfn == devfn)
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break;
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}
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if (i == ARRAY_SIZE(dnv_ir_lut)) {
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printk(BIOS_WARNING, "%s: no entry\n", __func__);
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goto dnv_get_ir_done;
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}
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switch (dnv_ir_lut[i].ir) {
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case 0:
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ir = config->ir00_routing;
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break;
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case 1:
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ir = config->ir01_routing;
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break;
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case 2:
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ir = config->ir02_routing;
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break;
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case 3:
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ir = config->ir03_routing;
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break;
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case 4:
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ir = config->ir04_routing;
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break;
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case 5:
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ir = config->ir05_routing;
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break;
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case 6:
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ir = config->ir06_routing;
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break;
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case 7:
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ir = config->ir07_routing;
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break;
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case 8:
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ir = config->ir08_routing;
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break;
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case 9:
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ir = config->ir09_routing;
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break;
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case 10:
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ir = config->ir10_routing;
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break;
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case 11:
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ir = config->ir11_routing;
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break;
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case 12:
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ir = config->ir12_routing;
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break;
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default:
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printk(BIOS_ERR, "%s: invalid ir %d for entry %d\n", __func__, dnv_ir_lut[i].ir,
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i);
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goto dnv_get_ir_done;
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}
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ir >>= (pin - 1) * 4;
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ir &= 0xf;
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switch (ir) {
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case 0:
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line = config->pirqa_routing;
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break;
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case 1:
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line = config->pirqb_routing;
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break;
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case 2:
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line = config->pirqc_routing;
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break;
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case 3:
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line = config->pirqd_routing;
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break;
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case 4:
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line = config->pirqe_routing;
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break;
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case 5:
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line = config->pirqf_routing;
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break;
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case 6:
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line = config->pirqg_routing;
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break;
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case 7:
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line = config->pirqh_routing;
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break;
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default:
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printk(BIOS_ERR, "%s: invalid ir pirq %d for entry %d\n", __func__, ir, i);
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break;
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}
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dnv_get_ir_done:
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return line;
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}
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/*
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* PCI devices have the INT_LINE (0x3C) and INT_PIN (0x3D) registers which
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* report interrupt routing information to operating systems and drivers. The
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* INT_PIN register is generally read only and reports which interrupt pin
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* A - D it uses. The INT_LINE register is configurable and reports which IRQ
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* (generally the PIC IRQs 1 - 15) it will use. This needs to take interrupt
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* pin swizzling on devices that are downstream on a PCI bridge into account.
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*/
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static u8 dnv_get_int_line(struct device *irq_dev)
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{
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config_t *config;
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struct device *targ_dev = NULL;
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uint16_t parent_bdf = 0;
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int8_t original_int_pin = 0, new_int_pin = 0, swiz_int_pin = 0;
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uint8_t int_line = 0xff;
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if (irq_dev->path.type != DEVICE_PATH_PCI || !irq_dev->enabled) {
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printk(BIOS_ERR, "%s for non pci device?\n", __func__);
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goto dnv_get_int_line_done;
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}
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/*
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* Get the INT_PIN swizzled up to the root port if necessary
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* using the existing coreboot pci_device code
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*/
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original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
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new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev);
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if (targ_dev == NULL || new_int_pin < 1)
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goto dnv_get_int_line_done;
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printk(BIOS_DEBUG, "%s: irq_dev %s, targ_dev %s:\n", __func__, dev_path(irq_dev),
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dev_path(targ_dev));
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printk(BIOS_DEBUG, "%s: std swizzle %s from %c to %c\n", __func__, dev_path(targ_dev),
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'@' + original_int_pin, '@' + new_int_pin);
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/* Swizzle this device if needed */
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config = targ_dev->chip_info;
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parent_bdf = targ_dev->path.pci.devfn | targ_dev->bus->secondary << 8;
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if (is_dnv_swizzled_rp(parent_bdf) && irq_dev != targ_dev) {
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swiz_int_pin = dnv_get_swizzled_pin(config, parent_bdf, new_int_pin);
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printk(BIOS_DEBUG, "%s: dnv swizzle %s from %c to %c\n", __func__,
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dev_path(targ_dev), '@' + new_int_pin, '@' + swiz_int_pin);
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} else {
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swiz_int_pin = new_int_pin;
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}
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/* Look up the routing for the pin */
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int_line = dnv_get_ir(config, parent_bdf, swiz_int_pin);
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dnv_get_int_line_done:
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printk(BIOS_DEBUG, "\tINT_LINE\t\t: %d\n", int_line);
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return int_line;
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}
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/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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* 0x02 - 0010 = Reserved
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* 0x03 - 0011 = IRQ3
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* 0x04 - 0100 = IRQ4
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* 0x05 - 0101 = IRQ5
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* 0x06 - 0110 = IRQ6
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* 0x07 - 0111 = IRQ7
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* 0x08 - 1000 = Reserved
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* 0x09 - 1001 = IRQ9
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* 0x0A - 1010 = IRQ10
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* 0x0B - 1011 = IRQ11
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* 0x0C - 1100 = IRQ12
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* 0x0D - 1101 = Reserved
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* 0x0E - 1110 = IRQ14
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* 0x0F - 1111 = IRQ15
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* PIRQ[n]_ROUT[7] - PIRQ Routing Control
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* 0x80 - The PIRQ is not routed.
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*/
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static void pch_pirq_init(struct device *dev)
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{
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struct device *irq_dev;
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/* Get the chip configuration */
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config_t *config = config_of(dev);
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/* Initialize PIRQ Routings */
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write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT),
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config->pirqa_routing);
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write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT),
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config->pirqb_routing);
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write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT),
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config->pirqc_routing);
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write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT),
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config->pirqd_routing);
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write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT),
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config->pirqe_routing);
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write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT),
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config->pirqf_routing);
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write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT),
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config->pirqg_routing);
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write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT),
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config->pirqh_routing);
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/* Initialize device's Interrupt Routings */
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00),
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config->ir00_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01),
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config->ir01_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02),
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config->ir02_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03),
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config->ir03_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04),
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config->ir04_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05),
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config->ir05_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06),
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config->ir06_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07),
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config->ir07_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08),
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config->ir08_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09),
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config->ir09_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10),
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config->ir10_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11),
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config->ir11_routing);
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write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12),
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config->ir12_routing);
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/* Initialize device's Interrupt Polarity Control */
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write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0),
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config->ipc0);
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write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1),
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config->ipc1);
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write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2),
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config->ipc2);
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write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3),
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config->ipc3);
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for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
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int devfn = irq_dev->path.pci.devfn;
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u8 int_pin = 0, int_line = 0;
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if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
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continue;
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int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
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int_line = dnv_get_int_line(irq_dev);
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printk(BIOS_DEBUG, "%s: %02x:%02x.%d pin %d int line %d\n", __func__,
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irq_dev->bus->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line);
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pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
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}
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}
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static void pci_p2sb_read_resources(struct device *dev)
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{
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struct resource *res;
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/* Add MMIO resource
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* Use 0xda as an unused index for PCR BAR.
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*/
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res = new_resource(dev, 0xda);
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res->base = DEFAULT_PCR_BASE;
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res->size = 16 * 1024 * 1024; /* 16MB PCR config space */
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res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
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IORESOURCE_ASSIGNED;
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printk(BIOS_DEBUG,
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"Adding P2SB PCR config space BAR 0x%08lx-0x%08lx.\n",
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(unsigned long)(res->base),
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(unsigned long)(res->base + res->size));
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/* Add MMIO resource
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* Use 0xdb as an unused index for IOAPIC.
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*/
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res = new_resource(dev, 0xdb); /* IOAPIC */
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res->base = IO_APIC_ADDR;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static void pch_enable_serial_irqs(struct device *dev)
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{
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/* Set packet length and toggle silent mode bit for one frame. */
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
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#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
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pci_write_config8(dev, SERIRQ_CNTL,
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|
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
|
|
#endif
|
|
}
|
|
|
|
static void lpc_init(struct device *dev)
|
|
{
|
|
printk(BIOS_DEBUG, "pch: %s\n", __func__);
|
|
|
|
/* Get the base address */
|
|
|
|
/* Set the value for PCI command register. */
|
|
pci_write_config16(dev, PCI_COMMAND,
|
|
PCI_COMMAND_SPECIAL | PCI_COMMAND_MASTER |
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
|
|
|
|
/* Serial IRQ initialization. */
|
|
pch_enable_serial_irqs(dev);
|
|
|
|
/* IO APIC initialization. */
|
|
pch_enable_ioapic(dev);
|
|
|
|
/* Setup the PIRQ. */
|
|
pch_pirq_init(dev);
|
|
}
|
|
|
|
static void pch_lpc_add_mmio_resources(struct device *dev) { /* TODO */ }
|
|
|
|
static void pch_lpc_add_io_resources(struct device *dev)
|
|
{
|
|
struct resource *res;
|
|
u8 io_index = 0;
|
|
|
|
/* Add an extra subtractive resource for both memory and I/O. */
|
|
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
|
res->base = 0;
|
|
res->size = 0x1000;
|
|
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
|
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
|
|
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
|
res->base = 0xff000000;
|
|
res->size = 0x01000000; /* 16 MB for flash */
|
|
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
|
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
}
|
|
|
|
static void lpc_read_resources(struct device *dev)
|
|
{
|
|
/* Get the normal PCI resources of this device. */
|
|
pci_dev_read_resources(dev);
|
|
|
|
/* Add non-standard MMIO resources. */
|
|
pch_lpc_add_mmio_resources(dev);
|
|
|
|
/* Add IO resources. */
|
|
pch_lpc_add_io_resources(dev);
|
|
|
|
/* Add MMIO resource for IOAPIC. */
|
|
pci_p2sb_read_resources(dev);
|
|
}
|
|
|
|
static void pch_decode_init(struct device *dev) { /* TODO */ }
|
|
|
|
static void lpc_enable_resources(struct device *dev)
|
|
{
|
|
pch_decode_init(dev);
|
|
pci_dev_enable_resources(dev);
|
|
}
|
|
|
|
/* Set bit in Function Disable register to hide this device */
|
|
static void pch_hide_devfn(uint32_t devfn) { /* TODO */ }
|
|
|
|
void southcluster_enable_dev(struct device *dev)
|
|
{
|
|
u16 reg16;
|
|
|
|
if (!dev->enabled) {
|
|
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
|
|
|
|
/* Ensure memory, io, and bus master are all disabled */
|
|
reg16 = pci_read_config16(dev, PCI_COMMAND);
|
|
reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_IO);
|
|
pci_write_config16(dev, PCI_COMMAND, reg16);
|
|
|
|
/* Hide this device if possible */
|
|
pch_hide_devfn(dev->path.pci.devfn);
|
|
} else {
|
|
/* Enable SERR */
|
|
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
|
|
}
|
|
}
|
|
|
|
static struct device_operations device_ops = {
|
|
.read_resources = lpc_read_resources,
|
|
.set_resources = pci_dev_set_resources,
|
|
#if CONFIG(HAVE_ACPI_TABLES)
|
|
.write_acpi_tables = southcluster_write_acpi_tables,
|
|
#endif
|
|
.enable_resources = lpc_enable_resources,
|
|
.init = lpc_init,
|
|
.enable = southcluster_enable_dev,
|
|
.scan_bus = scan_static_bus,
|
|
.ops_pci = &soc_pci_ops,
|
|
};
|
|
|
|
static const struct pci_driver lpc_driver __pci_driver = {
|
|
.ops = &device_ops,
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_DENVERTON_LPC,
|
|
};
|
|
|
|
static void finalize_chipset(void *unused)
|
|
{
|
|
apm_control(APM_CNT_FINALIZE);
|
|
}
|
|
|
|
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
|
|
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL);
|