coreboot-kgpe-d16/src/soc/intel/icelake/uart.c
Aamir Bohra 17cfba6fd4 soc/intel/common/block/uart: Update the UART PCI device reference
This implementation revises the UART PCI device reference in common
UART driver. The SOC functions have been aligned to provide the UART
PCI device reference using pcidev_path_on_root.

The uart_get_device() return type is changed, and files in which
it gets used are updated.

Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-04 15:16:50 +00:00

70 lines
1.9 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017-2018 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/pci_def.h>
#include <intelblocks/gpio.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pcr.h>
#include <intelblocks/uart.h>
#include <soc/iomap.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
const struct uart_gpio_pad_config uart_gpio_pads[] = {
{
.console_index = 0,
.gpios = {
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
},
},
{
.console_index = 1,
.gpios = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
},
},
{
.console_index = 2,
.gpios = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
},
}
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}