55208409bc
This change configures reset config for all pads routed to IOAPIC as PLTRST. This is required to ensure that the internal logic of the GPIO gets reset any time the platform enters S3 or powers off and avoids any interrupt storms on boot-up. BUG=b:129933011 TEST=Verified that there are no interrupt storms on boot-up from S5. Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> |
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| .. | ||
| spd | ||
| variants | ||
| acpi_tables.c | ||
| board_info.txt | ||
| bootblock.c | ||
| chromeos-16MiB.fmd | ||
| chromeos.c | ||
| chromeos.fmd | ||
| dsdt.asl | ||
| ec.c | ||
| Kconfig | ||
| Kconfig.name | ||
| mainboard.c | ||
| Makefile.inc | ||
| ramstage.c | ||
| romstage.c | ||
| smihandler.c | ||