coreboot-kgpe-d16/src/soc/rockchip
Vadim Bendebury 5554d1cf8a rk3399: add ability to configure SPI5
This defines mux settings for the GPIO bank responsible for SPI
interface #5.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
     communicate with the EC on gru: pressing Ctrl-U during boot
     allows to start Chrome OS from the SD card.

Change-Id: Ibc2293b5662892f7b275434f9a672ef68edf4f9e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4f92452
Original-Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346630
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15030
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:20:18 +02:00
..
common rockchip: revert the common tsadc header 2016-05-18 20:14:39 +02:00
rk3288 rk3288: Remove duplicate timestamp_init() 2016-06-06 21:54:34 +02:00
rk3399 rk3399: add ability to configure SPI5 2016-06-08 23:20:18 +02:00