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Duncan Laurie 559e947306 acpi_device: Add support for writing ACPI Device Properties
The recent ACPI specification extensions have formally defined a
method for describing device information with a key=value format that
is modeled after the Devicetree/DTS format using a special crafted
object named _DSD with a specific UUID for this format.

There are three defined Device Property types: Integers, Strings, and
References.  It is also possible to have arrays of these properties
under one key=value pair.  Strings and References are both represented
as character arrays but result in different generated ACPI OpCodes.

Various helpers are provided for writing the Device Property header
(to fill in the object name and UUID) and footer (to fill in the
property count and device length values) as well as for writing the
different Device Property types.  A specific helper is provided for
writing the defined GPIO binding Device Property that is used to allow
GPIOs to be referred to by name rather than resource index.

This is all documented in the _DSD Device Properties UUID document:
http://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf

This will be used by device drivers to provide device properties that
are consumed by the operating system.  Devicetree bindings are often
described in the linux kernel at Documentation/devicetree/bindings/

A sample driver here has an input GPIO that it needs to describe to
the kernel driver:

chip.h:
  struct drivers_generic_sample_config {
    struct acpi_gpio mode_gpio;
  };

sample.c:
  static void acpi_fill_ssdt_generator(struct device *dev) {
    struct drivers_generic_sample_config *config = dev->chip_info;
    const char *path = acpi_device_path(dev);
    ...
    acpi_device_write_gpio(&config->mode_gpio);
    ...
    acpi_dp_write_header();
    acpi_dp_write_gpio("mode-gpio", path, 0, 0, 0);
    acpi_dp_write_footer();
    ...
  }

devicetree.cb:
  device pci 1f.0 on
    chip drivers/generic/sample
      register "mode_gpio" = "ACPI_GPIO_INPUT(GPP_B1)"
      device generic 0 on end
    end
  end

SSDT.dsl:
  Name (_CRS, ResourceTemplate () {
    GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionInputOnly,
            "\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 25 }
  })
  Name (_DSD, Package () {
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
    Package () {
      Package () {"mode-gpio", Package () { \_SB.PCI0.LPCB, 0, 0, 1 }}
    }
  })

Change-Id: I93ffd09e59d05c09e38693e221a87085469be3ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14937
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28 03:48:55 +02:00
3rdparty 3rdparty/blobs: add more Qualcomm stubs 2016-05-10 21:22:28 +02:00
Documentation Documentation/Intel: Update the documentation 2016-05-18 19:47:16 +02:00
payloads arm64: Add stack dump to exception handler 2016-05-24 20:51:28 +02:00
src acpi_device: Add support for writing ACPI Device Properties 2016-05-28 03:48:55 +02:00
util cbfstool: Move cbfs_file_get_header to fit.c 2016-05-26 23:51:08 +02:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore .gitignore: add build and libpayload dirs for nvramcui payload 2016-05-03 04:16:45 +02:00
.gitmodules git modules: rename git submodules to avoid hierarchies 2016-02-11 20:55:55 +01:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb 2016-05-26 23:52:57 +02:00
Makefile Makefile: Update payload clean targets 2016-03-09 17:01:56 +01:00
Makefile.inc splash: Put the suffix of splash file to CBFS name 2016-05-26 23:48:02 +02:00
README
toolchain.inc toolchain.inc: test IASL by version string instead of number 2016-03-04 16:36:25 +01:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.