Krzysztof Sywula bb0cf01911 soc/intel/common/block: Add WHL 2-core SKU ... There are two SKUs of Whiskey Lake W0, 2-core and 4-core. Change-Id: Ia9b2707568702a5fbae3e9495ca53df34613a542 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/28111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>		2018-08-20 15:50:57 +00:00
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amd	soc/amd/common/block/pi/agesawarapper.c: Use find_image()	2018-08-17 21:11:07 +00:00
broadcom	soc/broadcom/cygnus: Increase romstage SRAM size in memlayout	2018-08-13 12:16:32 +00:00
cavium	soc/cavium/cn81xx: Fix minor things	2018-08-10 23:24:56 +00:00
imgtec	soc/imgtec/pistachio: Get rid of device_t	2018-06-04 09:18:19 +00:00
intel	soc/intel/common/block: Add WHL 2-core SKU	2018-08-20 15:50:57 +00:00
lowrisc	riscv: add support for modifying compiler options	2018-07-17 18:09:43 +00:00
mediatek	arm64: Factor out common parts of romstage execution flow	2018-08-17 21:29:46 +00:00
nvidia	arm64: Remove set_cntfrq() function	2018-08-10 04:16:06 +00:00
qualcomm	drivers/i2c: Add i2c TPM support for different stages	2018-08-10 23:25:52 +00:00
rockchip	drivers/i2c: Add i2c TPM support for different stages	2018-08-10 23:25:52 +00:00
samsung	src: Fix typo	2018-08-10 21:25:53 +00:00
sifive	sifive/fu540: add empty sdram init and size functions	2018-07-18 07:54:54 +00:00
ucb	riscv: add support for modifying compiler options	2018-07-17 18:09:43 +00:00