903ce25040
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
77 lines
1.8 KiB
Text
77 lines
1.8 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_AMD_LAMAR
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BINARYPI_LEGACY_WRAPPER
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select CPU_AMD_PI_00630F01
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select NORTHBRIDGE_AMD_PI_00630F01
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select SOUTHBRIDGE_AMD_PI_BOLTON
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select SUPERIO_FINTEK_F81216H
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_8192
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select GFXUMA
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config MAINBOARD_DIR
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string
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default amd/lamar
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config MAINBOARD_PART_NUMBER
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string
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default "DB-FP3"
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config MAINBOARD_SERIAL_NUMBER
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string
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default "52198A"
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config MAX_CPUS
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int
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default 4
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config HUDSON_XHCI_FWM_FILE
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string
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default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin"
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config AZ_PIN
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hex
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default 0x02
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config ENABLE_DP3_DAUGHTER_CARD_IN_J120
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bool "Use J120 as an additional graphics port"
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default n
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help
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The PCI Express slot at J120 can be configured as an additional
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DisplayPort connector using an adapter card from AMD or as a normal
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PCI Express (x4) slot.
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By default, the connector is configured as a PCI Express (x4) slot.
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Select this option to enable the slot for use with one of AMD's
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passive graphics port expander cards (only available from AMD).
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endif # BOARD_AMD_LAMAR
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