c02c34e886
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 One Laptop per Child, Association, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef VX800_H
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#define VX800_H 1
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#ifndef __PRE_RAM__
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#include <device/device.h>
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static inline void vx800_noop(device_t dev)
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{
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}
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#endif
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//#define REV_B0 0x10
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#define REV_B1 0x11
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//#define REV_B2 0x12
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#define REV_B3 0x13
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#define REV_B4 0x14
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//#define REV_B2 0xB4
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#define REV_B0 0x00
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#define REV_B2 0x01
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/* VGA stuff */
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#define SR_INDEX 0x3c4
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#define SR_DATA 0x3c5
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#define CRTM_INDEX 0x3b4
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#define CRTM_DATA 0x3b5
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#define CRTC_INDEX 0x3d4
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#define CRTC_DATA 0x3d5
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/* Memory Controller Registers */
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#define RANK0_END 0x40
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#define RANK1_END 0x41
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#define RANK2_END 0x42
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#define RANK3_END 0x43
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#define RANK0_START 0x48
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#define RANK1_START 0x49
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#define RANK2_START 0x4a
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#define RANK3_START 0x4b
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#define DDR_PAGE_CTL 0x69
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#define DRAM_REFRESH_COUNTER 0x6a
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#define DRAM_MISC_CTL 0x6b
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#define CH_A_DQS_OUTPUT_DELAY 0x70
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#define CH_A_MD_OUTPUT_DELAY 0x71
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/* RAM Init Commands */
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#define RAM_COMMAND_NORMAL 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x4
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/* IDE specific bits */
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#define IDE_MODE_REG 0x09
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#define IDE0_NATIVE_MODE (1 << 0)
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#define IDE1_NATIVE_MODE (1 << 2)
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/* These are default addresses according to Via */
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#define IDE0_DATA_ADDR 0x1f0
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#define IDE0_CONTROL_ADDR 0x3f4
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#define IDE1_DATA_ADDR 0x170
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#define IDE1_CONTROL_ADDR 0x370
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/* By Award default, Via default is 0xCC0 */
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#define BUS_MASTER_ADDR 0xfe00
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#define CHANNEL_ENABLE_REG 0x40
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#define ENABLE_IDE0 (1 << 0)
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#define ENABLE_IDE1 (1 << 1)
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#define VX800_ACPI_IO_BASE 0x0400
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#define NB_APIC_REG 0,0,5,
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#define NB_PXPTRF_REG NB_APIC_REG
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#define NB_MSGC_REG NB_APIC_REG
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#define NB_HOST_REG 0,0,2,
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#define NB_P6IF_REG NB_HOST_REG
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#define NB_DRAMC_REG 0,0,3,
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#define NB_PMU_REG 0,0,4,
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#define NB_VLINK_REG 0,0,7,
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#define NB_PEG_BRIDGE_REG 0,2, 0,
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#define NB_D3F0_REG 0,3, 0,
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#define NB_D3F1_REG 0,3, 1,
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#define SB_LPC_REG 0,0x11,0,
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#define SB_VLINK_REG 0,0x11,7,
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#define SB_SATA_REG 0,0xf, 0,
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#define SB_IDEC_REG 0,0xf, 0,
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#define SB_P2PB_REG 0,0x13, 0,
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#define SB_USB0_REG 0,0x10, 0,
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#define SB_USB1_REG 0,0x10, 1,
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#define SB_USB2_REG 0,0x10, 2,
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#define SB_EHCI_REG 0,0x10, 4,
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#define VX800SB_APIC_ID 0x4
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#define VX800SB_APIC_BASE 0xfec00000ULL
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#define VX800SB_APIC_DATA_OFFSET 0x10
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#define VX800SB_APIC_ENTRY_NUMBER 0x40
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#define VX800_D0F5_MMCONFIG_MBAR 0x61
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#endif
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