56c7dc7972
A while back coreboot was changed to read the subsystem IDs from devicetree.cb to allow each onboard PCI device to have its own subsystem id. When we originally branched, this was not the case, and the sandybridge/ivybridge mainboards have not been updated yet. Also, drop the subsystem ID from Emerald Lake 2, since it's not a Google device. Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1042 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> |
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.. | ||
acpi | ||
acpi_tables.c | ||
chip.h | ||
chromeos.c | ||
cmos.layout | ||
devicetree.cb | ||
dsdt.asl | ||
ec.c | ||
ec.h | ||
fadt.c | ||
gpio.h | ||
hda_verb.h | ||
Kconfig | ||
mainboard.c | ||
mainboard_smi.c | ||
Makefile.inc | ||
onboard.h | ||
romstage.c | ||
thermal.h |