131d9f5190
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
170 lines
4.8 KiB
C
170 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOUTHBRIDGE_INTEL_I82801JX_I82801JX_H
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#define SOUTHBRIDGE_INTEL_I82801JX_I82801JX_H
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#define DEFAULT_TBAR ((u8 *)0xfed1b000)
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#include <southbridge/intel/common/rcba.h>
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#define DEFAULT_PMBASE 0x00000500
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#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)
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#define DEFAULT_GPIOBASE 0x00000580
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#define APM_CNT 0xb2
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#define GP_IO_USE_SEL 0x00
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#define GP_IO_SEL 0x04
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#define GP_LVL 0x0c
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#define GPO_BLINK 0x18
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#define GPI_INV 0x2c
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#define GP_IO_USE_SEL2 0x30
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#define GP_IO_SEL2 0x34
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#define GP_LVL2 0x38
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#define DEBUG_PERIODIC_SMIS 0
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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/* D31:F0 LPC bridge */
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#define D31F0_ACPI_CNTL 0x44
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#define ACPI_CNTL D31F0_ACPI_CNTL
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#define D31F0_GPIO_BASE 0x48
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#define D31F0_GPIO_CNTL 0x4c
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#define D31F0_PIRQA_ROUT 0x60
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#define D31F0_PIRQB_ROUT 0x61
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#define D31F0_PIRQC_ROUT 0x62
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#define D31F0_PIRQD_ROUT 0x63
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#define D31F0_SERIRQ_CNTL 0x64
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#define D31F0_PIRQE_ROUT 0x68
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#define D31F0_PIRQF_ROUT 0x69
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#define D31F0_PIRQG_ROUT 0x6a
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#define D31F0_PIRQH_ROUT 0x6b
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#define D31F0_LPC_IODEC 0x80
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#define D31F0_LPC_EN 0x82
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#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
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#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
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#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
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#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
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#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
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#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
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#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
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#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
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#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
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#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
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#define D31F0_GEN1_DEC 0x84
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#define D31F0_GEN2_DEC 0x88
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#define D31F0_GEN3_DEC 0x8c
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#define D31F0_GEN4_DEC 0x90
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#define D31F0_C5_EXIT_TIMING 0xa8
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#define D31F0_CxSTATE_CNF 0xa9
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#define D31F0_C4TIMING_CNT 0xaa
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#define D31F0_GPIO_ROUT 0xb8
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/* D31:F2 SATA */
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#define D31F2_IDE_TIM_PRI 0x40
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#define D31F2_IDE_TIM_SEC 0x42
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#define D31F2_SIDX 0xa0
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#define D31F2_SDAT 0xa4
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/* D30:F0 PCI-to-PCI bridge */
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#define D30F0_SMLT 0x1b
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/* D28:F0-5 PCIe root ports */
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#define D28Fx_XCAP 0x42
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#define D28Fx_SLCAP 0x54
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/* PCI Configuration Space (D31:F3): SMBus */
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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/* HOSTC bits */
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#define I2C_EN (1 << 2)
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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#define RCBA_V0CTL 0x0014
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#define RCBA_V1CAP 0x001c
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#define RCBA_V1CTL 0x0020
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#define RCBA_V1STS 0x0026
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#define RCBA_PAT 0x0030
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#define RCBA_CIR1 0x0088
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#define RCBA_ESD 0x0104
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#define RCBA_ULD 0x0110
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#define RCBA_ULBA 0x0118
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#define RCBA_LCAP 0x01a4
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#define RCBA_LCTL 0x01a8
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#define RCBA_LSTS 0x01aa
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#define RCBA_CIR2 0x01f4
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#define RCBA_CIR3 0x01fc
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#define RCBA_BCR 0x0220
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#define RCBA_DMIC 0x0234
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#define RCBA_RPFN 0x0238
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#define RCBA_CIR13 0x0f20
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#define RCBA_CIR5 0x1d40
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#define RCBA_DMC 0x2010
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#define RCBA_CIR6 0x2024
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#define RCBA_CIR7 0x2034
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#define RCBA_HPTC 0x3404
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#define GCS 0x3410
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#define RCBA_BUC 0x3414
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#define RCBA_FD 0x3418 /* Function Disable, see below. */
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#define RCBA_CG 0x341c
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#define RCBA_FDSW 0x3420
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#define RCBA_CIR8 0x3430
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#define RCBA_CIR9 0x350c
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#define RCBA_CIR10 0x352c
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#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */
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#define D31IP 0x3100 /* 32bit */
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#define D30IP 0x3104 /* 32bit R0: does not generate interrupt */
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#define D29IP 0x3108 /* 32bit */
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#define D28IP 0x310c /* 32bit */
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#define D27IP 0x3110 /* 32bit */
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#define D26IP 0x3114 /* 32bit */
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#define D25IP 0x3114 /* 32bit */
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#define D31IR 0x3140 /* 16bit */
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#define D30IR 0x3142 /* 16bit R0: does not generate interrupt */
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#define D29IR 0x3144 /* 16bit */
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#define D28IR 0x3146 /* 16bit */
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#define D27IR 0x3148 /* 16bit */
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#define D26IR 0x314c /* 16bit */
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#define D25IR 0x3150 /* 16bit */
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#define OIC 0x31ff /* 8bit */
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#define BUC_LAND (1 << 5) /* LAN */
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#define FD_SAD2 (1 << 25) /* SATA #2 */
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#define FD_TTD (1 << 24) /* Thermal Throttle */
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#define FD_PE6D (1 << 21) /* PCIe root port 6 */
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#define FD_PE5D (1 << 20) /* PCIe root port 5 */
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#define FD_PE4D (1 << 19) /* PCIe root port 4 */
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#define FD_PE3D (1 << 18) /* PCIe root port 3 */
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#define FD_PE2D (1 << 17) /* PCIe root port 2 */
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#define FD_PE1D (1 << 16) /* PCIe root port 1 */
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#define FD_EHCI1D (1 << 15) /* EHCI #1 */
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#define FD_LBD (1 << 14) /* LPC bridge */
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#define FD_EHCI2D (1 << 13) /* EHCI #2 */
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#define FD_U5D (1 << 12) /* UHCI #5 */
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#define FD_U4D (1 << 11) /* UHCI #4 */
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#define FD_U3D (1 << 10) /* UHCI #3 */
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#define FD_U2D (1 << 9) /* UHCI #2 */
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#define FD_U1D (1 << 8) /* UHCI #1 */
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#define FD_U6D (1 << 7) /* UHCI #6 */
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#define FD_HDAD (1 << 4) /* HD audio */
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#define FD_SD (1 << 3) /* SMBus */
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#define FD_SAD1 (1 << 2) /* SATA #1 */
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#ifndef __ACPI__
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#include <device/pci_ops.h>
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void i82801jx_lpc_setup(void);
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void i82801jx_setup_bars(void);
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void i82801jx_early_init(void);
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#endif
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#endif
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