616f394d36
The inclusion of reg_script_run_on_dev() allows
for removing some of the chained reg_scripts just
to set up the device context. Use the new reg_script
function in those cases.
BUG=None
BRANCH=None
TEST=Built and booted. Didn't see any bizarre dmesg or coreboot
console output.
Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438
Signed-off-by: Aaron Durbin <adurbin@chromium.og>
Reviewed-on: https://chromium-review.googlesource.com/179541
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5009
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
125 lines
4 KiB
C
125 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <reg_script.h>
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#include <baytrail/iosf.h>
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#include <baytrail/nvs.h>
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#include <baytrail/ramstage.h>
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static const struct reg_script scc_start_dll[] = {
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/* Configure master DLL. */
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REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000),
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/* Configure Swing,FSM for Master DLL */
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REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133),
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/* Run+Local Reset on Master DLL */
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REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933),
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REG_SCRIPT_END,
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};
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static const struct reg_script scc_after_dll[] = {
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/* Configure Write Path */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad),
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/* Configure Read Path */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad),
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/* eMMC 4.5 TX and RX DLL */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0),
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/* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0),
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/*
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* iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01
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* iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01
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*/
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REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5),
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/* Enable IOSF Snoop */
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REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)),
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/* SDIO 3V Support. */
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REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30),
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REG_SCRIPT_END,
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};
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void baytrail_init_scc(void)
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{
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uint32_t dll_values;
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printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n");
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/* Common Sideband Initialization for SCC */
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reg_script_run(scc_start_dll);
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/* Override Slave Path - populate DLL settings. */
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dll_values = iosf_score_read(0x496c) & 0x7ffff;
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dll_values |= iosf_score_read(0x4950) & ~0xfffff;
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iosf_score_write(0x4950, dll_values | (1 << 19));
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reg_script_run(scc_after_dll);
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}
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void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
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{
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struct reg_script ops[] = {
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/* Disable PCI interrupt, enable Memory and Bus Master */
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REG_PCI_OR32(PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
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/* Enable ACPI mode */
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REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg,
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SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN),
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REG_SCRIPT_END
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};
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struct resource *bar;
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global_nvs_t *gnvs;
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/* Find ACPI NVS to update BARs */
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gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (!gnvs) {
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printk(BIOS_ERR, "Unable to locate Global NVS\n");
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return;
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}
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/* Save BAR0 and BAR1 to ACPI NVS */
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bar = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (bar)
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gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base;
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bar = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (bar)
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gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base;
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/* Device is enabled in ACPI mode */
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gnvs->dev.scc_en[nvs_index] = 1;
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/* Put device in ACPI mode */
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reg_script_run_on_dev(dev, ops);
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}
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