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Rex-BC Chen 5841bf3ec4 soc/mediatek/mt8186: Prevent early USB wakeup
The MT8186 platform fails to suspend due to premature wakeup by USB.

In MT8186, we use low level latch to keep USB wakeup signal. However,
hardware could latch a wrong signal if it debounces more than one time.
As a result, it would enable wakeup function too early.

To prevent this issue, we do the following modification:
- Delay about 100 us to enable wakeup function in kernel drivers [1].
- To guarantee 100 us is enough, we need to disable the USB debounce by
  default in coreboot.

According to section register 0x404 and 0x420 in
"(CODA) MT8169_PERICFG_REG.xls" which is only for MediaTek internal use:
The current default value of debounce register for MT8186 USB IP0 and
IP1 is incorrect. The reason we add in coreboot is that the default
value should be correct when SoC is booting up.

This modification is only for MT8186. The subsequent SoCs will adjust
the wakeup function to correct register value by default.

[1]: 0d8cfeeef3f5 (usb: xhci-mtk: fix random remote wakeup)

TEST=after stress test, not found premature wakeup by USB
BUG=b:228773975

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I296c4491c5959670a39fa8bd6ef987557bbc459f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63858
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-02 14:02:38 +00:00
3rdparty tests: update CMocka to stable-1.1 2022-04-19 13:00:36 +00:00
Documentation cpu/x86/64bit: Generate static page tables from an assembly file 2022-04-25 14:00:41 +00:00
LICENSES treewide: Remove trailing whitespace 2021-02-17 17:30:05 +00:00
configs src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard 2022-02-11 20:14:55 +00:00
payloads payloads/depthcharge: enable LP_CHROMEOS in depthcharge 2022-04-19 13:03:00 +00:00
spd spd/lp5: Add new part MT62F2G32D8DR-031 2022-03-10 15:16:52 +00:00
src soc/mediatek/mt8186: Prevent early USB wakeup 2022-05-02 14:02:38 +00:00
tests lib: Check for non-existent DIMMs in check_if_dimm_changed 2022-04-20 06:57:21 +00:00
util util/cbmem: fix an unused parameter issue in timestamp_get 2022-04-27 00:32:29 +00:00
.checkpatch.conf checkpatch.conf: Disable gerrit change ID for coreboot 2022-04-12 20:39:50 +00:00
.clang-format
.editorconfig
.gitignore .gitignore: Ignore .test/.dependencies globally 2020-10-31 18:21:36 +00:00
.gitmodules tests: update CMocka to stable-1.1 2022-04-19 13:00:36 +00:00
.gitreview
.mailmap .mailmap: Add a .mailmap file for git 2022-03-08 18:53:47 +00:00
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING
MAINTAINERS MAINTAINERS: Add myself as maintainer of mc_ehl boards 2022-04-29 13:14:24 +00:00
Makefile Makefile: Clean up old targets 2022-03-31 17:37:59 +00:00
Makefile.inc Makefile.inc: Add fmap_config.h as a dependency to cbfs-struct generation 2022-04-20 10:08:33 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
toolchain.inc build system: immediately report what users are supposed to look into 2021-10-18 16:39:25 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.