f8248f38a1
According ADL EDS to update the PCH and CPU PCIe RP table. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
34 lines
840 B
C
34 lines
840 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <intelblocks/pcie_rp.h>
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#include <soc/pci_devs.h>
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#include <soc/pcie.h>
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static const struct pcie_rp_group pch_lp_rp_groups[] = {
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{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
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{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
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{ 0 }
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};
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const struct pcie_rp_group *get_pch_pcie_rp_table(void)
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{
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return pch_lp_rp_groups;
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}
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/*
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* ADL-P FSP define CPU RP as below:
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* RP1: PEG60 : 0:6:0 : x4 CPU Slot
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* RP2: PEG10 : 0:1:0 : x8 CPU Slot
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* RP3: PEG62 : 0:6:2 : x4 CPU Slot
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*/
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static const struct pcie_rp_group cpu_rp_groups[] = {
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{ .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 },
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{ .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1 },
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{ .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 },
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{ 0 }
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};
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const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
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{
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return cpu_rp_groups;
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}
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