291b58f06e
Add MMIO offsets for USB2 and USB3 port status registers, for both north (TCSS) and south (PCH) XHCI controllers; implement soc_get_xhci_usb_info() to return the appropriate entries for elog. Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
44 lines
1.3 KiB
C
44 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_type.h>
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#include <intelblocks/xhci.h>
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#include <soc/pci_devs.h>
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/*
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* Information obtained from Intel doc# 630094, ADL-P PCH EDS Vol. 2,
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* as well as doc# 626817, ADL-P PCH EDS Vol. 1
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*/
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#define PCH_XHCI_USB2_PORT_STATUS_REG 0x480
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#define PCH_XHCI_USB3_PORT_STATUS_REG 0x540
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#define PCH_XHCI_USB2_PORT_NUM 10
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#define PCH_XHCI_USB3_PORT_NUM 4
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#define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480
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#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x540
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#define TCSS_XHCI_USB2_PORT_NUM 10
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#define TCSS_XHCI_USB3_PORT_NUM 4
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static const struct xhci_usb_info usb_info = {
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.usb2_port_status_reg = PCH_XHCI_USB2_PORT_STATUS_REG,
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.num_usb2_ports = PCH_XHCI_USB2_PORT_NUM,
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.usb3_port_status_reg = PCH_XHCI_USB3_PORT_STATUS_REG,
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.num_usb3_ports = PCH_XHCI_USB3_PORT_NUM,
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};
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static const struct xhci_usb_info tcss_usb_info = {
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.usb2_port_status_reg = TCSS_XHCI_USB2_PORT_STATUS_REG,
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.num_usb2_ports = TCSS_XHCI_USB2_PORT_NUM,
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.usb3_port_status_reg = TCSS_XHCI_USB3_PORT_STATUS_REG,
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.num_usb3_ports = TCSS_XHCI_USB3_PORT_NUM,
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};
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const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
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{
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if (xhci_dev == PCH_DEVFN_XHCI)
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return &usb_info;
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else if (xhci_dev == SA_DEVFN_TCSS_XHCI)
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return &tcss_usb_info;
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return NULL;
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}
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