68f688896c
This reverts commit 5fbe788bae.
This commit was submitted without its parent being submitted,
resulting in coreboot not building.
Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
161 lines
3.6 KiB
C
161 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include "pmutil.h"
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#define DEBUG_PERIODIC_SMIS 0
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static u16 pmbase;
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u16 get_pmbase(void)
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{
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return pmbase;
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}
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void southbridge_smm_init(void)
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{
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u32 smi_en;
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u16 pm1_en;
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u32 gpe0_en;
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#if IS_ENABLED(CONFIG_ELOG)
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/* Log events from chipset before clearing */
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pch_log_state();
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#endif
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printk(BIOS_DEBUG, "Initializing southbridge SMI...");
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pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
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D31F0_PMBASE) & 0xff80;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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smi_en = inl(pmbase + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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printk(BIOS_DEBUG, "\n");
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dump_smi_status(reset_smi_status());
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dump_pm1_status(reset_pm1_status());
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dump_gpe0_status(reset_gpe0_status());
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dump_alt_gp_smi_status(reset_alt_gp_smi_status());
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dump_tco_status(reset_tco_status());
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/* Disable GPE0 PME_B0 */
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gpe0_en = inl(pmbase + GPE0_EN);
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gpe0_en &= ~PME_B0_EN;
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outl(gpe0_en, pmbase + GPE0_EN);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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outw(pm1_en, pmbase + PM1_EN);
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/* Enable SMI generation:
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* - on TCO events
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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*/
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smi_en = 0; /* reset SMI enables */
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#if 0
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smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
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#endif
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smi_en |= TCO_EN;
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smi_en |= APMC_EN;
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
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* periodic SMIs.
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*/
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smi_en |= PERIODIC_EN;
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#endif
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smi_en |= SLP_SMI_EN;
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#if 0
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smi_en |= BIOS_EN;
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#endif
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/* The following need to be on for SMIs to happen */
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smi_en |= EOS | GBL_SMI_EN;
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outl(smi_en, pmbase + SMI_EN);
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}
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void southbridge_trigger_smi(void)
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{
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/**
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* There are several methods of raising a controlled SMI# via
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* software, among them:
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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* I'm not too worried about the better of the methods at the moment
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*/
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/* raise an SMI interrupt */
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printk(BIOS_SPEW, " ... raise SMI#\n");
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outb(0x00, 0xb2);
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}
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void southbridge_clear_smi_status(void)
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{
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/* Clear SMI status */
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reset_smi_status();
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/* Clear PM1 status */
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reset_pm1_status();
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/* Set EOS bit so other SMIs can occur. */
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smi_set_eos();
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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/*
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* Issue SMI to set the gnvs pointer in SMM.
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* tcg and smi1 are unused.
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*
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* EAX = APM_CNT_GNVS_UPDATE
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* EBX = gnvs pointer
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* EDX = APM_CNT
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*/
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asm volatile (
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"outb %%al, %%dx\n\t"
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: /* ignore result */
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: "a" (APM_CNT_GNVS_UPDATE),
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"b" ((u32)gnvs),
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"d" (APM_CNT)
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);
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}
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