coreboot-kgpe-d16/src/soc
Julien Viard de Galbert 595202c304 soc/intel/denverton_ns: Add ACPI T-States and P-States
Also make soc_get_tss_table public and weak instead of static
in intelblock so it can be overridden in denverton.

Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-28 13:33:30 +00:00
..
amd soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout 2019-01-23 14:56:43 +00:00
cavium cbmem_top: Fix comment and remove upper limit 2019-01-24 13:54:21 +00:00
imgtec (console,drivers/uart)/Kconfig: Fix dependencies 2018-11-21 22:49:48 +00:00
intel soc/intel/denverton_ns: Add ACPI T-States and P-States 2019-01-28 13:33:30 +00:00
mediatek mediatek/mt8183: Move some initialization into mt8183_early_init 2019-01-24 13:53:16 +00:00
nvidia console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
qualcomm console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
rockchip console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
samsung soc/samsung/exynos5420: Disable BOOTBLOCK_CONSOLE 2019-01-16 11:07:11 +00:00
sifive riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00
ucb riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00