595688a3d6
The flush L1D to L2 operation was only being used when loading romstage from bootblock. However, when the FSP-M component is loaded no code coherency actions are taken. I suspect this is because the FSP-M component is larger than the 24KiB L1D and the entry point is early in the image. Thus, when loading the FSP-M component the earlier part of the image is flushed out to L2 in the process of loading the latter part of the component. Also, once verstage is introduced the same code coherency actions need to be taken as well. Therefore, position the apollolake code to handle all these cases. Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14210 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <arch/cpu.h>
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#include <bootblock_common.h>
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#include <device/pci.h>
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#include <soc/bootblock.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/uart.h>
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void asmlinkage bootblock_c_entry(void)
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{
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device_t dev = NB_DEV_ROOT;
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/* Set PCI Express BAR */
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pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
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dev = P2SB_DEV;
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/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
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pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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/* Call lib/bootblock.c main */
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main();
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}
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void bootblock_soc_early_init(void)
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{
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/* Prepare UART for serial console. */
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if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
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soc_console_uart_init();
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}
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