Ronald G. Minnich 5965cba3dc RISCV: Clean up the common architectural code ... This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload, entering main() with no supporting assembly code for startup. The Harvey port is not complete so it just panics but ... it gets started. We provide a standard payload function that takes a pointer argument and makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual memory setup code. We now use the _stack and _estack from memlayout so we know where things are. As time goes on maybe we can kill all the magic numbers. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17058 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>		2016-10-24 20:25:04 +02:00
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board_info.txt
devicetree.cb
Kconfig	Kconfig: lay groundwork for not assuming SPI flash boot device	2016-08-18 06:18:21 +02:00
Kconfig.name
mainboard.c	riscv and power8: Convert printk/while(1) to die	2016-10-15 00:24:46 +02:00
Makefile.inc	riscv: Use the generic src/lib/bootblock.c	2016-10-15 00:26:28 +02:00
memlayout.ld	RISCV: Clean up the common architectural code	2016-10-24 20:25:04 +02:00
rom_media.c	spike-riscv: Look for the CBFS in RAM	2016-07-14 18:24:34 +02:00
romstage.c
spike_util.c	riscv: Clean up {qemu,spike}_util	2016-10-15 00:25:05 +02:00
uart.c	riscv-spike: Replace custom UART with a memory-mapped 8250	2016-06-12 12:43:37 +02:00