ac87a9804b
Add PMC pci driver on top of PMC common code, also include pmc init code reference from skylake. Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 - 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <intelblocks/gpio.h>
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#include <intelblocks/pcr.h>
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#include <soc/pcr_ids.h>
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static const struct reset_mapping rst_map[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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};
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static const struct reset_mapping rst_map_com0[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
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};
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static const struct pad_community cnl_communities[] = {
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{ /* GPP A, B, G */
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.port = PID_GPIOCOM0,
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.first_pad = GPP_A0,
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.last_pad = GPP_G7,
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.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_ABG",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map_com0,
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.num_reset_vals = ARRAY_SIZE(rst_map_com0),
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}, { /* GPP D, F, H */
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.port = PID_GPIOCOM1,
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.first_pad = GPP_D0,
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.last_pad = GPP_H23,
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.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_DFH",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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}, { /* GPD */
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.port = PID_GPIOCOM2,
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.first_pad = GPD0,
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.last_pad = GPD11,
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.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPD",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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}, { /* GPP C, E */
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.port = PID_GPIOCOM4,
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.first_pad = GPP_C0,
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.last_pad = GPP_E23,
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.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_CE",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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}
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};
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const struct pad_community *soc_gpio_get_community(size_t *num_communities)
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{
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*num_communities = ARRAY_SIZE(cnl_communities);
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return cnl_communities;
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}
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const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
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{
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static const struct pmc_to_gpio_route routes[] = {
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{ GPP_A, GPP_A },
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{ GPP_B, GPP_B },
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{ GPP_C, GPP_C },
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{ GPP_D, GPP_D },
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{ GPP_E, GPP_E },
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{ GPP_F, GPP_F },
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{ GPP_G, GPP_G },
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{ GPP_H, GPP_H },
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{ GPD, GPD },
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};
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*num = ARRAY_SIZE(routes);
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return routes;
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}
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