5a45c9529a
In order to support probing I2C devices when the controller is in ACPI mode the mainboard needs to decalre them in the proper scope with the address/interrupt information. The touchpad devices are ATML0000/ELAN0000 and the touchscreen is ATML0001 so they can be distinguished in userland scripts based on ID. There is also a special "ISTP" node that indicates whether the devices is a touchpad (=1) or touchscreen (=0) in case this is useful to drivers. These names may not be final but they are a starting point and can be easily changed. Atmel devices also have a bootloader mode which needs to be declared as a separate device. Unfortunately it does not work as expected to have multiple I2cSerialBus() resources declared in a single device and have it select properly, even with the use of StartDependentFn(), so bootloader devices are declared separately. The original devices are left in \_SB scope and are only enabled if the I2C controllers are in PCI mode. The new devices are only enabled if the I2C controllers are in ACPI mode. BUG=chrome-os-partner:24380 BRANCH=baytrail TEST=manual 1) Ensure there is no change in functionality by default and that the devices are still probed by chromeos_laptop in the kernel. 2) Enable lpss_acpi_mode=1 in devicetree.cb and kernel changes to add _HID entries for devices in appropriate drivers. Ensure that the devices are probed successfully. Further changes are needed to the chromeos-touch-firmware scripts to load config and update firmware based on the new ACPI _HID entries. 3) Put touchpad in bootloader mode (by flashing bad firmware) and ensure that it is detected at address 0x25 and the firmware is able to be updated. Change-Id: I5b9b47ddc94474a677497271e963f62cb09438e0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182259 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5045 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
60 lines
1.6 KiB
Text
60 lines
1.6 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ENABLE_TPM
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x05, // DSDT revision: ACPI v5.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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// Some generic macros
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#include <soc/intel/baytrail/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/baytrail/acpi/globalnvs.asl>
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//#include "acpi/thermal.asl"
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#include <soc/intel/baytrail/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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//#include <soc/intel/baytrail/acpi/northcluster.asl>
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#include <soc/intel/baytrail/acpi/southcluster.asl>
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}
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/* Dynamic Platform Thermal Framework */
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#include "acpi/dptf.asl"
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}
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#include "acpi/chromeos.asl"
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <soc/intel/baytrail/acpi/sleepstates.asl>
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#include "acpi/mainboard.asl"
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}
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