coreboot-kgpe-d16/src
Stanley Wu 5a702653cd mb/google/dedede/var/boten: Adjust p-sensor detect distance to 20mm
P-sensor vendor fine-tune detect distance as 20mm for WWAN SAR table switch.

BUG=b:179000150
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected.
     un-approach:
       => register address: 0x01 value: 0x00
     approach:
       => register address: 0x01 value: 0x02
     Confirm WWAN SAR table work as expected.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I659721e60aa0766ed4c277dae43ded222e18ad1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51343
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 00:33:28 +00:00
..
acpi
arch
commonlib cbfs: Add cbfs_alloc() primitive and combine cbfs_load() and cbfs_map() 2021-03-08 22:31:43 +00:00
console
cpu src/cpu/x86: Add helper mp_run_on_all_aps 2021-03-11 15:53:58 +00:00
device
drivers driver/intel/fsp2_0: Allow function to run serially on all APs 2021-03-11 15:54:04 +00:00
ec
include src/cpu/x86: Add helper mp_run_on_all_aps 2021-03-11 15:53:58 +00:00
lib cbfs: Add cbfs_alloc() primitive and combine cbfs_load() and cbfs_map() 2021-03-08 22:31:43 +00:00
mainboard mb/google/dedede/var/boten: Adjust p-sensor detect distance to 20mm 2021-03-12 00:33:28 +00:00
northbridge nb/intel/haswell: Finalize northbridge in ramstage 2021-03-10 10:59:36 +00:00
security security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset EC 2021-03-05 10:57:01 +00:00
soc soc/amd: move warm reset flag function prototypes to common code 2021-03-11 15:11:20 +00:00
southbridge nb/intel/haswell: Finalize northbridge in ramstage 2021-03-10 10:59:36 +00:00
superio
vendorcode vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02 2021-03-10 20:30:20 +00:00
Kconfig