Jonathan Neuschäfer 84bf089f6a Documentation/mainboard: Add emulation/spike-riscv.md

Move the usage instructions from their ad-hoc place in Kconfig.name to
the Documentation directory, and expand them a bit.

Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>

2018-10-29 11:19:34 +00:00

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Spike RISC-V emulator

Spike, also known as riscv-isa-sim, is a commonly used RISC-V emulator.

Installation

Download riscv-fesvr and riscv-isa-sim from https://github.com/riscv/
Apply the two patches in https://github.com/riscv/riscv-isa-sim/pull/53, which are necessary in order to have a serial console
Compile riscv-fesvr and then riscv-isa-sim

Building coreboot and running it in Spike

Configure coreboot and run make as usual
Run util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf to convert coreboot to an ELF that Spike can load
Run spike -m1024 build/coreboot.elf

719 B Raw Blame History

Spike RISC-V emulator

Installation

Building coreboot and running it in Spike

719 B

Raw Blame History