Jonathan Zhang 5bb89e7f0c vendorcode/intel/FSP2_0/CPX-SP: update to ww36 ... Intel CPX-SP FSP ww36 release has following changes: * Update FSP header version to change among FSP releases. * Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11 (OEM strings) generation. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-09-08 05:36:34 +00:00
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amd	{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent	2020-09-01 03:06:04 +00:00
cavium	{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent	2020-09-01 03:06:04 +00:00
eltan	Kconfig: Escape variable to accommodate new Kconfig versions	2020-06-19 15:29:04 +00:00
google	vendorcode/google: Add error handling	2020-08-31 06:28:45 +00:00
intel	vendorcode/intel/FSP2_0/CPX-SP: update to ww36	2020-09-08 05:36:34 +00:00
siemens	src: Fix up ##-commented SPDX headers	2020-06-01 17:01:13 +00:00
Makefile.inc