coreboot-kgpe-d16/src/include/cpu/x86
Kevin O'Connor 5bb9fd6e4d Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg.  This reduces boot time by
about 1 second on epia-cn.

This patch also adds a MTRRphysMaskValid bit definition.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19 06:32:35 +00:00
..
bist.h We call this cache as ram everywhere, so let's call it the same in Kconfig 2010-08-30 17:53:13 +00:00
cache.h AMD Fam10 code breaks with gcc 4.5.0. 2010-09-17 21:38:40 +00:00
car.h Factor out common CAR asm snippets. 2010-10-01 21:46:04 +00:00
lapic.h drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more 2010-03-28 21:26:54 +00:00
lapic_def.h - Renamed cpu header files 2004-10-14 20:13:01 +00:00
msr.h AMD Fam10 code breaks with gcc 4.5.0. 2010-09-17 21:38:40 +00:00
mtrr.h Now that the VIA code is run above 1Meg (like other boards), it should 2011-01-19 06:32:35 +00:00
multiboot.h Generate multiboot tables from coreboot tables. 2010-09-13 14:47:22 +00:00
name.h Factor out fill_processor_name() and strcpy() functions. 2010-09-29 09:54:16 +00:00
pae.h Since some people disapprove of white space cleanups mixed in regular commits 2010-04-27 06:56:47 +00:00
post_code.h drop "arch/asm.h" and "arch/intel.h" and create "cpu/x86/post_code.h" 2010-04-25 20:42:02 +00:00
smm.h SMM for AMD K8 Part 1/2 2010-12-18 23:29:37 +00:00
stack.h Since some people disapprove of white space cleanups mixed in regular commits 2010-04-27 06:56:47 +00:00
tsc.h drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more 2010-03-28 21:26:54 +00:00