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Arthur Heymans 5d0a93d5e7 mb/ga-g41m-es2l: Correctly configure PCI IRQ in ACPI
Obtained from vendor bios DSDT, under "Device (HUB0),
Name (_ADR, 0x001E0000)".

The schematics also indicate that the INTA-D are hardwired to these
PIRQ lines.

Change-Id: I8e1c6cb986a2b345a5e1fddd454c7fb12fb8256a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17099
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21 23:58:15 +01:00
3rdparty 3rdparty/vboot: update to latest master 2016-11-10 00:57:27 +01:00
Documentation Documentation: Add Kconfig document 2016-11-13 21:41:44 +01:00
payloads Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU 2016-10-27 18:52:30 +02:00
src mb/ga-g41m-es2l: Correctly configure PCI IRQ in ACPI 2016-11-21 23:58:15 +01:00
util util/inteltool: Fix bay trail ahci device 2016-11-21 23:38:40 +01:00
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MAINTAINERS MAINTAINERS: Add lowrisc files to RISC-V 2016-11-12 19:30:26 +01:00
Makefile Makefile: Allow inclusion of source files from 3rdparty/ 2016-10-29 01:34:06 +02:00
Makefile.inc Makefile.inc: export VARIANT_DIR as top-level variable 2016-11-18 20:28:37 +01:00
README Remove extra newlines from the end of all coreboot files. 2016-07-31 18:19:33 +02:00
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
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README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.