Lee Leahy 5e07a7e474 soc/intel/quark: Switch to using serial routines for FSP ... Switch from passing FSP the serial port address to passing FSP the serial port output routine. This enables coreboot to use any UART in the system and also log the FSP output. TEST=Build and run on Galileo Gen2 Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>		2016-08-10 22:31:52 +02:00
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broadcom/cygnus	Remove non-ascii & unprintable characters	2016-08-01 21:44:45 +02:00
dmp/vortex86ex	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
imgtec/pistachio	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
intel	soc/intel/quark: Switch to using serial routines for FSP	2016-08-10 22:31:52 +02:00
marvell	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
mediatek/mt8173	Remove extra newlines from the end of all coreboot files.	2016-07-31 18:19:33 +02:00
nvidia	soc/nvidia/tegra210: remove unused spi boot device support	2016-08-09 01:33:03 +02:00
qualcomm	soc/qualcomm/ipq40xx: Use block mode for I2C	2016-08-09 00:22:35 +02:00
rdc/r8610	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
rockchip	rockchip/rk3399: sdram: correct read obs and set DQS driver register	2016-08-09 00:22:51 +02:00
samsung	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
ucb/riscv	arch/riscv: Move CBMEM into RAM	2016-07-15 03:01:02 +02:00