Michael Niewöhner 5e779f9a6c mb/intel/saddlebrook: migrate to FSP 2.0 ... This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) TODO: - testing Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923 Reviewed-by: Michael Niewöhner Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-10-26 15:15:33 +00:00
..
acpi
spd	mb/{asrock,intel,purism}: Copy channel arrays separately	2019-08-20 15:18:10 +00:00
acpi_tables.c
board_info.txt
bootblock.c
cmos.default
cmos.layout
devicetree.cb	mb/intel/saddlebrook: migrate to FSP 2.0	2019-10-26 15:15:33 +00:00
dsdt.asl
gpio.h
Kconfig	mb/intel/saddlebrook: migrate to FSP 2.0	2019-10-26 15:15:33 +00:00
Kconfig.name
Makefile.inc	mb/intel/saddlebrook: Refactor to get rid of pei_data	2019-05-07 15:57:15 +00:00
ramstage.c	mb/intel/saddlebrook: migrate to FSP 2.0	2019-10-26 15:15:33 +00:00
romstage.c	mb/intel/saddlebrook: migrate to FSP 2.0	2019-10-26 15:15:33 +00:00