Wim Vervoorn 5f2adfe1a3 soc/intel/skylake: Control fixed IO decode from devicetree ... The current implementation doesn't allow custom values for the LPC IO decodes and IO enables. Add the lpc_ioe and lpc_iod values. If they are not zero, they will be used instead of the current handling for COMA and COMB. BUG=N/A TEST=tested on facebook monolith Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38748 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-03-18 16:27:01 +00:00
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amd	soc/amd/picasso: Set I2C clock reference to 150MHz	2020-03-17 22:47:20 +00:00
cavium	soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>	2019-12-19 05:38:43 +00:00
intel	soc/intel/skylake: Control fixed IO decode from devicetree	2020-03-18 16:27:01 +00:00
mediatek	vboot: remove extraneous vboot_recovery_mode_memory_retrain	2020-03-12 07:39:47 +00:00
nvidia	src: Remove unneeded 'include <arch/cache.h>'	2020-03-10 20:39:50 +00:00
qualcomm	src: Remove unneeded 'include <arch/cache.h>'	2020-03-10 20:39:50 +00:00
rockchip	src: Remove unneeded 'include <arch/cache.h>'	2020-03-10 20:39:50 +00:00
samsung	soc/{samsung,sifive}: Fix typos	2020-02-24 13:01:15 +00:00
sifive	soc/{samsung,sifive}: Fix typos	2020-02-24 13:01:15 +00:00
ucb	mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.	2019-12-06 15:09:48 +00:00