coreboot-kgpe-d16/src/soc/intel/skylake/include
Patrick Rudolph 9a016236d4 soc/intel/skylake/vr_config: Add loadline defaults
In addition to zero IccMax specified by mainboard with socketed CPU, allow
a zero LoadLine default.
The SoC code will fill in the default AC/DC LoadLine values are per
datasheets:

* "7th Generation Intel® Processor Families for H Platforms, Vol 1"
  Document Number: 335190-003
* "7th Generation Intel® Processor Families for S Platforms and
  Intel ®Core™ X-Series Processor Family, Vol 1"
  Document Number: 335195-003

The AC/DC LoadLine is CPU and board specific.
TODO: Find out how to get the LoadLine from vendor firmware and find out
how to map those to different CPU LoadLines.

Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34938
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20 11:14:47 +00:00
..
fsp11/soc intel/fsp1_1: Drop remnants of pei_data 2019-05-07 15:59:10 +00:00
fsp20/soc soc/{amd,intel}/chip: Use local include for chip.h 2019-04-26 16:49:13 +00:00
soc soc/intel/skylake/vr_config: Add loadline defaults 2019-08-20 11:14:47 +00:00