Felix Held 60a4643d6f soc/amd/common: factor out SMU code from Picasso ... The SMU mailbox access code from Picasso can be reused in the next generation, so factor out the code to soc/amd/common/block/smu. Since the mailbox register offsets in the indirect address space, the number of arguments and the message IDs don't always match between different devices, keep those in the soc-specific directories. Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2020-11-15 16:48:38 +00:00
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amd	soc/amd/common: factor out SMU code from Picasso	2020-11-15 16:48:38 +00:00
cavium
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	soc/intel/cnl: enable ACPI CPPC entries generation	2020-11-14 18:54:35 +00:00
mediatek	soc/mediatek/mt8192: Do dram full calibration	2020-10-29 00:30:34 +00:00
nvidia	soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab	2020-11-09 10:31:32 +00:00
qualcomm	mrc_cache: Move code for triggering memory training into mrc_cache	2020-11-13 22:57:50 +00:00
rockchip	soc/rockchip/rk3288/include/soc/display.h: Add missing includes	2020-10-19 07:12:07 +00:00
samsung	src/soc/samsung: Move common headers to "common/include/soc"	2020-10-19 07:11:32 +00:00
sifive
ti
ucb