347 lines
12 KiB
Markdown
347 lines
12 KiB
Markdown
# vboot - Verified Boot Support
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Google's verified boot support consists of:
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* A root of trust
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* Special firmware layout
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* Firmware verification
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* Firmware measurements
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* A firmware update mechanism
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* Specific build flags
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* Signing the coreboot image
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Google's vboot verifies the firmware and places measurements within the TPM.
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- [List of supported Devices](list_vboot.md)
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***
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## Root of Trust
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When using vboot, the root-of-trust is basically the read-only portion of the
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SPI flash. The following items factor into the trust equation:
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* The GCC compiler must reliably translate the code into machine code
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without inserting any additional code (virus, backdoor, etc.)
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* The CPU must reliably execute the reset sequence and instructions as
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documented by the CPU manufacturer.
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* The SPI flash must provide only the code programmed into it to the CPU
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without providing any alternative reset vector or code sequence.
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* The SPI flash must honor the write-protect input and protect the specified
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portion of the SPI flash from all erase and write accesses.
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The firmware is typically protected using the write-protect pin on the SPI
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flash part and setting some of the write-protect bits in the status register
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during manufacturing. The protected area is platform specific and for x86
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platforms is typically 1/4th of the SPI flash part size.
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Because this portion of the SPI flash is hardware write protected, it is not
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possible to update this portion of the SPI flash in the field, without altering
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the system to eliminate the ground connection to the SPI flash write-protect pin.
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Without hardware modifications, this portion of the SPI flash maintains the
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manufactured state during the system's lifetime.
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***
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## Firmware Layout
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Several sections are added to the firmware layout to support vboot:
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* Read-only section
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* Google Binary Blob (GBB) area
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* Read/write section A
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* Read/write section B
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The following sections describe the various portions of the flash layout.
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### Read-Only Section
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The read-only section contains a coreboot file system (CBFS) that contains all
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of the boot firmware necessary to perform recovery for the system. This firmware
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is typically protected using the write-protect pin on the SPI flash part and
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setting some of the write-protect bits in the status register during
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manufacturing.
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The protected area is typically 1/4th of the SPI flash part size and must cover
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the entire read-only section which consists of:
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* Vital Product Data (VPD) area
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* Firmware ID area
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* Google Binary Blob (GBB) area
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* coreboot file system containing read-only recovery firmware
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### Google Binary Blob (GBB) Area
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The GBB area is part of the read-only section. This area contains a 4096 or 8192
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bit public root RSA key that is used to verify the *VBLOCK* area to obtain the
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firmware signing key.
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### Recovery Firmware
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The recovery firmware is contained within a coreboot file system and consists of:
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* reset vector
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* bootblock
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* verstage
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* romstage
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* postcar
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* ramstage
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* payload
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* flash map file
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* config file
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* processor specific files:
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* Microcode
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* fspm.bin
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* fsps.bin
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The recovery firmware is written during manufacturing and typically contains
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code to write the storage device (eMMC device or hard disk). The recovery image
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is usually contained on a socketed device such as a USB flash drive or an
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SD card. Depending upon the payload firmware doing the recovery, it may be
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possible for the user to interact with the system to specify the recovery
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image path. Part of the recovery is also to write the A and B areas of the SPI
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flash device to boot the system.
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### Read/Write Section
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The read/write sections contain an area which contains the firmware signing
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key and signature and an area containing a coreboot file system with a subset
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of the firmware. The firmware files in *FW_MAIN_A* and *FW_MAIN_B* are:
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* romstage
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* postcar
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* ramstage
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* payload
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* config file
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* processor specific files:
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* Microcode
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* fspm.bin
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* fsps.bin
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The firmware subset enables most issues to be fixed in the field with firmware
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updates. The firmware files handle memory and most of silicon initialization.
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These files also produce the tables which get passed to the operating system.
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***
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## Firmware Updates
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The read/write sections exist in one of three states:
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* Invalid
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* Ready to boot
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* Successfully booted
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Firmware updates are handled by the operating system by writing any read/write
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section that is not in the "successfully booted" state. Upon the next reboot,
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vboot determines the section to boot. If it finds one in the "ready to boot"
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state then it attempts to boot using that section. If the boot fails then
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vboot marks the section as invalid and attempts to fall back to a read/write
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section in the "successfully booted" state. If vboot is not able to find a
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section in the "successfully booted" state then vboot enters recovery mode.
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Only the operating system is able to transition a section from the
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"ready to boot" state to the "successfully booted" state.
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The transition is typically done after the operating system has been running
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for a while indicating that successful boot was possible and the operating
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system is stable.
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Note that as long as the SPI write protection is in place then the system
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is always recoverable. If the flash update fails then the system will continue
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to boot using the previous read/write area. The same is true if coreboot passes
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control to the payload or the operating system and then the boot fails. In the
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worst case, the SPI flash gets totally corrupted in which case vboot fails the
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signature checks and enters recovery mode. There are no times where the SPI
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flash is exposed and the reset vector or part of the recovery firmware gets
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corrupted.
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***
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## Build Flags
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The following *Kconfig* values need to be selected to enable vboot:
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* COLLECT_TIMESTAMPS
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* VBOOT
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The starting stage needs to be specified by selecting either
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VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE.
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If vboot starts in bootblock then vboot may be built as a separate stage by
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selecting `VBOOT_SEPARATE_VERSTAGE`. Additionally, if static RAM is too small
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to fit both verstage and romstage then selecting `VBOOT_RETURN_FROM_VERSTAGE`
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enables bootblock to reuse the RAM occupied by verstage for romstage.
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Non-volatile flash is needed for vboot operation. This flash area may be in
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CMOS, the EC, or in a read/write area of the SPI flash device.
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Select one of the following:
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* `VBOOT_VBNV_CMOS`
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* `VBOOT_VBNV_EC`
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* `VBOOT_VBNV_FLASH`
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More non-volatile storage features may be found in `security/vboot/Kconfig`.
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A TPM is also required for vboot operation.
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TPMs are available in `drivers/i2c/tpm` and `drivers/pc80/tpm`.
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In addition to adding the coreboot files into the read-only region,
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enabling vboot causes the build script to add the read/write files into
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coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
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**RO_REGION_ONLY**
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The files added to this list will only be placed in the read-only region and
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not into the read/write coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
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**VBOOT_ENABLE_CBFS_FALLBACK**
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Normally coreboot will use the active read/write coreboot file system for all
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of it's file access when VBOOT is active and is not in recovery mode.
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When the `VBOOT_ENABLE_CBFS_FALLBACK` option is enabled the cbfs file system will
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first try to locate a file in the active read/write file system. If the file
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doesn't exist here the file system will try to locate the file in the read-only
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file system.
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This option can be used to prevent duplication of static data. Files can be
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removed from the read/write partitions by adding them to the `RO_REGION_ONLY`
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config. If a file needs to be changed in a later stage simply remove it from
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this list.
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***
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## Signing the coreboot Image
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The following command script is an example of how to sign the coreboot image
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file. This script is used on the Intel Galileo board and creates the *GBB* area
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and inserts it into the coreboot image. It also updates the *VBLOCK* areas with
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the firmware signing key and the signature for the *FW_MAIN* firmware.
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More details are available in `3rdparty/vboot/README`.
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```bash
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#!/bin/sh
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#
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# The necessary tools were built and installed using the following commands:
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#
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# pushd 3rdparty/vboot
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# make
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# sudo make install
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# popd
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#
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# The keys were made using the following command
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#
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# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \
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# --output $PWD/keys
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#
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#
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# The "magic" numbers below are derived from the GBB section in
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# src/mainboard/intel/galileo/vboot.fmd.
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#
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# GBB Header Size: 0x80
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# GBB Offset: 0x611000, 4KiB block number: 1553 (0x611)
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# GBB Length: 0x7f000, 4KiB blocks: 127 (0x7f)
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# COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690)
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# COREBOOT Length: 0x170000, 4KiB blocks: 368 (0x170)
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#
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# 0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000
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#
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# Create the GBB area blob
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# Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size
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#
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gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
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#
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# Copy from the start of the flash to the GBB region into the signed flash
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# image.
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#
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# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB
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#
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dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
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if=build/coreboot.rom of=build/coreboot.signed.rom
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#
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# Append the empty GBB area to the coreboot.rom image.
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#
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# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB
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#
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dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
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of=build/coreboot.signed.rom
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#
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# Append the rest of the read-only region into the signed flash image.
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#
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# 1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area
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# 368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area
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#
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dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 count=368 \
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if=build/coreboot.rom of=build/coreboot.signed.rom
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#
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# Insert the HWID and public root and recovery RSA keys into the GBB area.
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#
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gbb_utility \
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--set --hwid='Galileo' \
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-r $PWD/keys/recovery_key.vbpubk \
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-k $PWD/keys/root_key.vbpubk \
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build/coreboot.signed.rom
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#
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# Sign the read/write firmware areas with the private signing key and update
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# the VBLOCK_A and VBLOCK_B regions.
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#
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3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
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build/coreboot.signed.rom \
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$PWD/keys \
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build/coreboot.signed.rom
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```
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***
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## Boot Flow
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The reset vector exist in the read-only area and points to the bootblock
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entry point. The only copy of the bootblock exists in the read-only area
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of the SPI flash. Verstage may be part of the bootblock or a separate stage.
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If separate then the bootblock loads verstage from the read-only area and
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transfers control to it.
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Upon first boot, verstage attempts to verify the read/write section A.
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It gets the public root key from the GBB area and uses that to verify the
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*VBLOCK* area in read-write section A. If the *VBLOCK* area is valid then it
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extracts the firmware signing key (1024-8192 bits) and uses that to verify
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the *FW_MAIN_A* area of read/write section A. If the verification is successful
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then verstage instructs coreboot to use the coreboot file system in read/write
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section A for the contents of the remaining boot firmware (romstage, postcar,
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ramstage and the payload).
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If verification fails for the read/write area and the other read/write area is
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not valid vboot falls back to the read-only area to boot into system recovery.
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***
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## Chromebook Special Features
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Google's Chromebooks have some special features:
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* Developer mode
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* Write-protect screw
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### Developer Mode
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Developer mode allows the user to use coreboot to boot another operating system.
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This may be a another (beta) version of Chrome OS, or another flavor of
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GNU/Linux. Use of developer mode does not void the system warranty. Upon entry
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into developer mode, all locally saved data on the system is lost.
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This prevents someone from entering developer mode to subvert the system
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security to access files on the local system or cloud.
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### Write Protect Screw
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Chromebooks have a write-protect screw which provides the ground to the
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write-protect pin of the SPI flash.
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Google specifically did this to allow the manufacturing line and advanced
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developers to re-write the entire SPI flash part. Once the screw is removed,
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any firmware may be placed on the device.
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However, accessing this screw requires opening the case and voids the
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system warranty!
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