2854f40668
Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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};
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static struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = baytrail_init_cpus,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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} else if (dev->path.type == DEVICE_PATH_PCI) {
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/* Handle south cluster enablement. */
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if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
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(dev->ops == NULL || dev->ops->enable == NULL)) {
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southcluster_enable_dev(dev);
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}
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}
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}
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/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
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static void soc_init(void *chip_info)
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{
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baytrail_init_pre_device(chip_info);
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}
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struct chip_operations soc_intel_baytrail_ops = {
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CHIP_NAME("Intel BayTrail SoC")
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.enable_dev = enable_dev,
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.init = soc_init,
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};
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struct pci_operations soc_pci_ops = {
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.set_subsystem = &pci_dev_set_subsystem,
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};
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