563fc0889f
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __INTEL_SMM_RELOC_H__
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#define __INTEL_SMM_RELOC_H__
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#include <console/console.h>
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#include <types.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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struct smm_relocation_params {
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uintptr_t ied_base;
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size_t ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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msr_t prmrr_base;
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msr_t prmrr_mask;
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msr_t uncore_prmrr_base;
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msr_t uncore_prmrr_mask;
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/*
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* The smm_save_state_in_msrs field indicates if SMM save state
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* locations live in MSRs. This indicates to the CPUs how to adjust
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* the SMMBASE and IEDBASE
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*/
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int smm_save_state_in_msrs;
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};
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extern struct smm_relocation_params smm_reloc_params;
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struct ied_header {
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char signature[10];
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u32 size;
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u8 reserved[34];
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} __packed;
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/* These helpers are for performing SMM relocation. */
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void northbridge_write_smram(u8 smram);
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void smm_lock(void);
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void smm_relocate(void);
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/* The initialization of the southbridge is split into 2 components. One is
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* for clearing the state in the SMM registers. The other is for enabling
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* SMIs. They are split so that other work between the 2 actions. */
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void smm_southbridge_clear_state(void);
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/* To be removed. */
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void smm_initialize(void);
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void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size);
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void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase);
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bool cpu_has_alternative_smrr(void);
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#define MSR_PRMRR_PHYS_BASE 0x1f4
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
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#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
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static inline void write_smrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static inline void write_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
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wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
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wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
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}
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static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG,
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"Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_prmrr_base.lo,
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relo_params->uncore_prmrr_mask.lo);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
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}
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#endif
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