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Paul Menzel 65377eba7f Makefile.inc: Disable compiler warning array-compare for GCC
gcc 12 fails the build with the warning below:

        CC         romstage/lib/cbfs.o
    src/lib/cbfs.c: In function 'switch_to_postram_cache':
    src/lib/cbfs.c:31:32: error: comparison between two arrays [-Werror=array-compare]
       31 |         if (_preram_cbfs_cache != _postram_cbfs_cache)
          |                                ^~
    src/lib/cbfs.c:31:32: note: use '&_preram_cbfs_cache[0] != &_postram_cbfs_cache[0]' to compare the addresses

Instead of following gcc’s suggestion, disable the warning for gcc as
requested by Julius [1]:

> Can we just set -Wno-array-compare instead? There's nothing illegal
> about that expression and as we can see in this case, there are
> perfectly reasonable cases where you might want to do something like
> that. On the other hand, I don't really see a realistic scenario where
> this warning could prevent a real problem (anyone who doesn't know
> that array1 == array2  doesn't compare the array elements in C
> shouldn't have any business submitting code to coreboot).

[1]: https://review.coreboot.org/c/coreboot/+/62827/1

Found-by: gcc-12 (Debian 12-20220313-1) 12.0.1 20220314 (experimental) [master r12-7638-g823b3b79cd2]
Found-by: gcc (Debian 12.1.0-7) 12.1.0
Change-Id: I322f7cc57dcca713141bddaaaed9ec034898754d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-02 21:16:52 +00:00
3rdparty Update vboot submodule to upstream main 2022-08-02 07:06:17 +00:00
Documentation mb/hp/z220_series: Improve the port for z220_sff_workstation 2022-07-30 18:39:31 +00:00
LICENSES treewide: Unify Google branding 2022-07-04 14:02:26 +00:00
configs configs: Update prodrive hermes 2022-07-14 12:48:20 +00:00
payloads payloads/tianocore/Makefile: Fix restoring default boot logo 2022-08-02 12:19:34 +00:00
spd util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina 2022-08-01 20:30:39 +00:00
src soc/intel/alderlake: Configure DDR5 Physical channel width to 64 2022-08-02 18:32:20 +00:00
tests tests: Adjust the order of header files to include 2022-07-14 23:08:24 +00:00
util util/cbfstool/elogtool: Support logging FW vboot info in elog 2022-08-02 07:06:52 +00:00
.checkpatch.conf checkpatch.conf: Disable gerrit change ID for coreboot 2022-04-12 20:39:50 +00:00
.clang-format
.editorconfig
.gitignore .gitignore: Ignore .cache directory & compile_commands.json 2022-07-06 00:33:48 +00:00
.gitmodules tests: update CMocka to stable-1.1 2022-04-19 13:00:36 +00:00
.gitreview
.mailmap
AUTHORS
COPYING
MAINTAINERS MAINTAINERS: Add M. Żygowski and M. Kopeć as MSI MS-7D25 maintainers 2022-07-28 10:13:01 +00:00
Makefile Makefile: Add util/kconfig/Makefile.real to nocompile list 2022-07-17 22:17:10 +00:00
Makefile.inc Makefile.inc: Disable compiler warning array-compare for GCC 2022-08-02 21:16:52 +00:00
README.md Treewide: Remove doxygen config files and targets 2022-05-28 01:24:51 +00:00
gnat.adc
toolchain.inc

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.