Eric Lai 65e4f7858e mb/google/drallion: add dummy SPD file ... Drallion will use soldered down memory. Add dummy spd file. BUG=b:139397313 BRANCH=N/A TEST=Build and check cbfs has the dummy spd.bin Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-08-28 09:19:53 +00:00
..
acpi	AUTHORS: Move src/acpi copyrights into AUTHORS file	2019-07-30 11:04:14 +00:00
arch	AUTHORS: Move src/arch/mips copyrights into AUTHORS file	2019-08-27 07:02:57 +00:00
commonlib	commonlib/region: Fix up overflow check in region_is_subregion()	2019-08-19 21:12:31 +00:00
console	Add definition for ENV_ROMSTAGE_OR_BEFORE to <rules.h>	2019-08-26 20:59:45 +00:00
cpu	intel/car: Use common TS_START_ROMSTAGE	2019-08-26 22:53:31 +00:00
device	Split MAYBE_STATIC to _BSS and _NONZERO variants	2019-08-26 20:56:29 +00:00
drivers	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00
ec	Split MAYBE_STATIC to _BSS and _NONZERO variants	2019-08-26 20:56:29 +00:00
include	x86: Introduce RESET_VECTOR_IN_RAM option	2019-08-26 22:53:07 +00:00
lib	arch/x86: Simplify <arch/early_variables.h>	2019-08-26 22:52:10 +00:00
mainboard	mb/google/drallion: add dummy SPD file	2019-08-28 09:19:53 +00:00
northbridge	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00
security	Split MAYBE_STATIC to _BSS and _NONZERO variants	2019-08-26 20:56:29 +00:00
soc	intel/baytrail: Use smm_subregion()	2019-08-27 16:14:48 +00:00
southbridge	amdfam10: Remove use of __PRE_RAM__	2019-08-26 02:08:42 +00:00
superio	smsc/superio/sio1007: Fix header name	2019-08-27 11:52:13 +00:00
vendorcode	vendorcode/eltan/security/lib: Always include cb_sha.c for bootblock	2019-08-26 13:46:13 +00:00
Kconfig	ACPI S3: Depend on RELOCATABLE_RAMSTAGE	2019-08-22 06:38:13 +00:00