coreboot-kgpe-d16/src/soc
Andrey Petrov 662da6cf7b soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26 02:06:45 +00:00
..
amd amd/common/acpi: move thermal zone to common location 2020-03-25 15:19:52 +00:00
cavium soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
intel soc/intel/xeon_sp: Refactor code to allow for additional CPUs types 2020-03-26 02:06:45 +00:00
mediatek soc/mediatek/mt8183: Fix wrong setting of DRS config 2020-03-18 16:47:06 +00:00
nvidia soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
qualcomm soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
rockchip soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
samsung soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
sifive soc: Remove copyright notices 2020-03-18 16:44:46 +00:00
ucb mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. 2019-12-06 15:09:48 +00:00