coreboot-kgpe-d16/src
Alexandru Gagniuc 665fca156c intel/amenia: Declare ChromeEC in devicetree.cb
This allows the chomeec driver to declare its resources so that IO
windows to LPC are opened up during resource allocation.

Change-Id: Ife98ecb4cbf5393493e6c71742de8d37953df548
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06 18:57:56 +02:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch arch/x86: Drop CBFS_BASE_ADDRESS 2016-05-03 11:41:55 +02:00
commonlib ensure correct byte ordering for cbfs segment list 2016-04-25 23:30:00 +02:00
console arch/x86: introduce postcar stage/phase 2016-03-23 14:24:30 +01:00
cpu cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE 2016-05-06 16:49:37 +02:00
device payloads: add iPXE 'payload' build 2016-04-13 17:45:37 +02:00
drivers drivers/xpowers: Switch to src/drivers/[X]/[Y]/ scheme 2016-05-04 22:14:44 +02:00
ec ec/google/chromeec/ec_commands.h: Include stdint.h 2016-05-06 18:57:13 +02:00
include cpu/x86/mp_init: reduce exposure of internal implementation 2016-05-06 16:47:54 +02:00
lib lib/reg_script: Fix braces 2016-05-05 19:41:29 +02:00
mainboard intel/amenia: Declare ChromeEC in devicetree.cb 2016-05-06 18:57:56 +02:00
northbridge rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
soc soc/apollolake/lpc_lib: Add utility to configure LPC pads 2016-05-06 18:56:22 +02:00
southbridge rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
superio superio/smsc/mec1308: Fix AddressMax value for SMBX mailbox 2016-04-13 23:39:28 +02:00
vendorcode vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.h 2016-05-03 22:53:20 +02:00
Kconfig lib/coreboot_table: use the architecture dependent table size 2016-05-02 20:03:34 +02:00