a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com)
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* Copyright (C) 2007 AMD
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stddef.h>
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#include <console/console.h>
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#include <device/pci_ehci.h>
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#include <arch/io.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <string.h>
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#include "ehci_debug.h"
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#include "ehci.h"
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#if !defined(__PRE_RAM__) && !defined(__SMM__)
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static struct device_operations *ehci_drv_ops;
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static struct device_operations ehci_dbg_ops;
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#endif
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int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
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{
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pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
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pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev = dbg_dev;
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#else
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device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev));
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#endif
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u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
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if (!pos)
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return -1;
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u32 cap = pci_read_config32(dev, pos);
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/* FIXME: We should remove static EHCI_BAR_INDEX. */
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u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1);
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if (dbg_bar != EHCI_BAR_INDEX)
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return -1;
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*base = CONFIG_EHCI_BAR;
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*dbg_offset = (cap>>16) & 0x1ffc;
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return 0;
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}
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void ehci_debug_select_port(unsigned int port)
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{
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pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
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pci_ehci_dbg_set_port(dbg_dev, port);
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}
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#if !defined(__PRE_RAM__) && !defined(__SMM__)
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static void pci_ehci_set_resources(struct device *dev)
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{
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struct resource *res;
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printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev));
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usbdebug_disable();
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if (ehci_drv_ops->set_resources)
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ehci_drv_ops->set_resources(dev);
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res = find_resource(dev, EHCI_BAR_INDEX);
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if (!res)
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return;
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usbdebug_re_enable((u32)res->base);
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report_resource_stored(dev, res, "");
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printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev));
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}
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void pci_ehci_read_resources(struct device *dev)
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{
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pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
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if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) {
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memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
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ehci_drv_ops = dev->ops;
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ehci_dbg_ops.set_resources = pci_ehci_set_resources;
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dev->ops = &ehci_dbg_ops;
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printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev));
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} else {
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printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev));
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}
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pci_dev_read_resources(dev);
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}
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#endif
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u8 *pci_ehci_base_regs(pci_devfn_t sdev)
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{
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#ifdef __SIMPLE_DEVICE__
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u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
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#else
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device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
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u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
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#endif
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return base + HC_LENGTH(read32(base));
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}
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