Indrek Kruusa 8e3464109e Changelog: ... * src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2006-08-03 16:48:18 +00:00
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amd	Changelog:	2006-08-03 16:48:18 +00:00
intel	- Renamed cpu header files	2004-10-14 20:13:01 +00:00
ppc	- First stab at getting the ppc ports building and working.	2004-11-18 22:38:08 +00:00
x86	new cache_as_ram support	2006-04-03 20:38:34 +00:00
cpu.h	- First stab at getting the ppc ports building and working.	2004-11-18 22:38:08 +00:00