c4986eb7f4
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
107 lines
2.8 KiB
C
107 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <bootstate.h>
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#include <chip.h>
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#include <intelblocks/chip.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <string.h>
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#define PCR_DMI_GCS 0x274C
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#define PCR_DMI_GCS_BILD (1 << 0)
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static void pmc_lockdown_cfg(const struct soc_intel_common_config *config)
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{
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uint8_t *pmcbase, reg8;
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uint32_t reg32, pmsyncreg;
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/* PMSYNC */
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pmcbase = pmc_mmio_regs();
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pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
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pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
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write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
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/* Lock down ABASE and sleep stretching policy */
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reg32 = read32(pmcbase + GEN_PMCON_B);
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reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
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write32(pmcbase + GEN_PMCON_B, reg32);
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if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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pmcbase = pmc_mmio_regs();
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reg8 = read8(pmcbase + GEN_PMCON_B);
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reg8 |= SMI_LOCK;
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write8(pmcbase + GEN_PMCON_B, reg8);
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}
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}
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static void dmi_lockdown_cfg(void)
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{
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/*
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* GCS reg of DMI
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*
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* When set, prevents GCS.BBS from being changed
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* GCS.BBS: (Boot BIOS Strap) This field determines the destination
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* of accesses to the BIOS memory range.
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* Bits Description
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* "0b": SPI
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* "1b": LPC/eSPI
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*/
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pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
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}
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static void fast_spi_lockdown_cfg(const struct soc_intel_common_config *config)
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{
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/* Set FAST_SPI opcode menu */
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fast_spi_set_opcode_menu();
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/* Discrete Lock Flash PR registers */
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fast_spi_pr_dlock();
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/* Lock FAST_SPIBAR */
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fast_spi_lock_bar();
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/* Set Bios Interface Lock, Bios Lock */
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if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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/* Bios Interface Lock */
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fast_spi_set_bios_interface_lock_down();
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/* Bios Lock */
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fast_spi_set_lock_enable();
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}
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}
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static void platform_lockdown_config(void *unused)
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{
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const struct soc_intel_common_config *common_config;
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common_config = chip_get_common_soc_structure();
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/* SPI lock down configuration */
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fast_spi_lockdown_cfg(common_config);
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/* DMI lock down configuration */
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dmi_lockdown_cfg();
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/* PMC lock down configuration */
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pmc_lockdown_cfg(common_config);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
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NULL);
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