coreboot-kgpe-d16/src
Hung-Te Lin 69eae2762f board/kukui: Support ADC value for NC
When the components like LCM ID are not installed (i.e., NC), ADC will
return some value with much larger variation from standard value (out of
the tolerance we set). To support that, we should check tolerance only
on non-NC voltages.

Also improve the error messages so we can see the ADC raw values
instead of simple assertion error (which makes debugging more difficult
since we have to build another firmware image just to print the values).

BUG=None
TEST=Booted on Kukui and got correct SKU ID for NC LCMID.
BRANCH=None

Change-Id: I8d00956e0e3b48ddbcaa505dd3ade24720c3b4ad
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32353
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 19:56:23 +00:00
..
acpi
arch arch/x86/car.ld: Also check mrc.bin heap for Ivybridge 2019-04-22 13:40:14 +00:00
commonlib commonlib/cbfs: Check for presence of CONFIG() macro 2019-04-08 18:52:38 +00:00
console coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
cpu nb/intel/haswell: Add an option for where verstage starts 2019-04-21 23:32:37 +00:00
device src: Fix remaining #include <timer.h> 2019-04-09 17:20:35 +00:00
drivers drivers/intel/fsp2_0: Set basename for FSP binaries 2019-04-21 23:35:45 +00:00
ec ec/google/wilco: Support board_id with EC provided ID 2019-04-18 23:43:06 +00:00
include smbios: Add type 17 device/bank locator override 2019-04-19 01:39:03 +00:00
lib src: Use #include <timer.h> when appropriate 2019-04-06 16:02:49 +00:00
mainboard board/kukui: Support ADC value for NC 2019-04-22 19:56:23 +00:00
northbridge nb/intel/haswell: Add an option for where verstage starts 2019-04-21 23:32:37 +00:00
security vboot: do not set VBSD_BOOT_FIRMWARE_WP_ENABLED flag 2019-04-11 11:23:33 +00:00
soc cpu/x86: Move checking for MTRR's as a proxy for proper CPU reset 2019-04-21 23:29:29 +00:00
southbridge nb/intel/haswell: Add an option for where verstage starts 2019-04-21 23:32:37 +00:00
superio src: Use 'include <string.h>' when appropriate 2019-03-20 20:27:51 +00:00
vendorcode vc/amd/agesa/f14: Add missing break statement 2019-04-07 03:27:52 +00:00
Kconfig x86/smbios: Untangle system and board tables 2019-03-16 16:22:16 +00:00