coreboot-kgpe-d16/src/soc/intel
Kein Yuan 1a3675ec02 baytrail: Add defines and functions for GPNCORE
BUG=chrome-os-partner:25159
BRANCH=firmware-rambi-5216.B
TEST=Build pass for Rambi

Original-Change-Id: I049f9254fe25aabf13d891579444bba2cfcf68c5
Original-Change-Id: Ib7c814660262e2507813ee5970190f98530dfe5e
Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197984
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit dd05055f2f74fc0e4875733c0e5dedcbae302bfa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iee01407a73bec420ab47d07524a3f1fd0f4d9817
Reviewed-on: http://review.coreboot.org/7892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30 19:32:32 +01:00
..
baytrail baytrail: Add defines and functions for GPNCORE 2014-12-30 19:32:32 +01:00
broadwell intel baytrail broadwell: Include microcode updates 2014-12-28 20:01:19 +01:00
common baytrail: Move HDA verb table to Intel SOC common directory 2014-10-22 03:35:13 +02:00
fsp_baytrail fsp_baytrail: Initialize LPC pads in bootblock for port 80 2014-12-19 18:43:08 +01:00
Kconfig baytrail: Move MRC cache code to a common directory 2014-10-22 03:33:20 +02:00
Makefile.inc fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip 2014-05-29 23:10:36 +02:00