be91398353
Startpoint was Intel d945gclf, which has same chipset and Gigabyte ga-g41m-es2l which has same Superio. What works and is tested: * PCI slot; * PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card; * onboard VGA output (only textmode implemented) with native graphic init; * 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset); * serial output during and after boot. What does not work: * resume from suspend (does not work for d945gclf either). Quirks: * The Realtek ethernet card requires a reset which currently also hardcodes a MAC adress. This board was only tested with the SeaBIOS payload due to flash size constraints (512KB) and with GNU/Linux. Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17033 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
53 lines
1.3 KiB
Text
53 lines
1.3 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20090419 // OEM revision
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)
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{
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// Some generic macros
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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// General Purpose Events
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//#include "acpi/gpe.asl"
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// mainboard specific devices
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#include "acpi/mainboard.asl"
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// Thermal Zone
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//#include "acpi/thermal.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/i945/acpi/i945.asl>
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#include <southbridge/intel/i82801gx/acpi/ich7.asl>
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}
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}
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/* Chipset specific sleep states */
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#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
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}
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