6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
105 lines
2.6 KiB
C
105 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Tiger Lake Processor PCH Datasheet
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* Document number: 575857
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* Chapter number: 4, 29
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*/
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/thermal.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
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#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
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#define CAM_CLK_EN (1 << 1)
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#define MIPI_CLK (1 << 0)
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#define HDPLL_CLK (0 << 0)
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static void pch_enable_isclk(void)
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{
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pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
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pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
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}
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static void pch_handle_sideband(config_t *config)
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{
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if (config->pch_isclk)
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pch_enable_isclk();
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}
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static void pch_finalize(void)
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{
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uint32_t reg32;
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uint8_t *pmcbase;
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config_t *config;
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uint8_t reg8;
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/* TCO Lock down */
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tco_lockdown();
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/* TODO: Add Thermal Configuration */
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/*
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* Disable ACPI PM timer based on dt policy
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*
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* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
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* just required to get to chip config. PCH_DEV_PMC is hidden by this
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* point and hence removed from the root bus. pcidev_path_on_root thus
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* returns NULL for PCH_DEV_PMC device.
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*/
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config = config_of_soc();
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pmcbase = pmc_mmio_regs();
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if (config->PmTimerDisabled) {
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reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
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reg8 |= (1 << 1);
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write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
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}
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/* Disable XTAL shutdown qualification for low power idle. */
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if (config->s0ix_enable) {
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reg32 = read32(pmcbase + CPPMVRIC);
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reg32 |= XTALSDQDIS;
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write32(pmcbase + CPPMVRIC, reg32);
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}
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pch_handle_sideband(config);
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pmc_clear_pmcon_sts();
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}
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static void soc_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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outb(APM_CNT_FINALIZE, APM_CNT);
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
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