6d20d0c140
Historically in coreboot, the PMC's fixed PCI resources were described by the System Agent (the MMIO resource), and eSPI/LPC (the I/O resource). This patch moves both of those to a new Intel SoC-specific function, soc_pmc_read_resources(). On TGL, this new function takes care of providing the MMIO and I/O resources for the PMC. BUG=b:156388055 TEST=verified on volteer that the resource allocator is aware of and does not touch these two resources: ("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1") Also verify that the MEM resource is described in the coreboot table: ("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved") Verified the memory range is also untouchable from Linux: ("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved") Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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.. | ||
acpi | ||
bootblock | ||
include/soc | ||
romstage | ||
acpi.c | ||
chip.c | ||
chip.h | ||
cpu.c | ||
elog.c | ||
espi.c | ||
finalize.c | ||
fsp_params.c | ||
gpio.c | ||
graphics.c | ||
gspi.c | ||
i2c.c | ||
Kconfig | ||
lockdown.c | ||
Makefile.inc | ||
me.c | ||
meminit.c | ||
p2sb.c | ||
pmc.c | ||
pmutil.c | ||
reset.c | ||
smihandler.c | ||
smmrelocate.c | ||
spi.c | ||
systemagent.c | ||
uart.c |